Ioana Graur

Process window OPC for reduced process variability and enhanced yield

As the industry moves toward 45nm technology node and beyond, further reduction of lithographic process window is anticipated. The consequence of this is twofold: first, the manufactured chip will have pattern sizes that are different from the designed pattern sizes and those variations may become more dominated by systematic components as the process windows shrink; second, smaller process windows will lead to yield loss as, at small dimensions, lithographic process windows are often constrained by catastrophic fails such as resist collapse or trench scumming, rather than by gradual pattern size variation. With this notion, Optical Proximity Correction (OPC) for future technology generations must evolve from the current single process point OPC to algorithms that provide an OPC solution optimized for process variability and yield. In this paper, a Process Window OPC (PWOPC) concept is discussed, along with its place in the design-to-manufacturing flow. Use of additional models for process corners, integration of process fails and algorithm optimization for a production-worthy flow are described. Results are presented for 65nm metal levels.

Alternating phase-shifted mask for logic gate levels, design, and mask manufacturing

While the benefits of alternating phase shifted masks in improving lithographic process windows at increased resolution are well known throughout the lithography community, broad implementation of this potentially powerful technique has been slow due to the inherent complexity of the layout design and mask manufacturing process. This paper will review a project undertaken at IBMs Semiconductor Research and Development Center and Mask Manufacturing and Development facility to understand the technical and logistical issues associated with the application of alternating phase shifted mask technology to the gate level of a full microprocessor chip. The work presented here depicts an important milestone toward integration of alternating phase shifted masks into the manufacturing process by demonstrating an automated design solution and yielding a functional alternating phase shifted mask. The design conversion of the microprocessor gate level to a conjugate twin shifter alternating phase shift layout was accomplished with IBMs internal design system that automatically scaled the design, added required phase regions, and resolved phase conflicts. The subsequent fabrication of a nearly defect free phase shifted mask, as verified by SEM based die to die inspection, highlights the maturity of the alternating phase shifted mask manufacturing process in IBMs internal mask facility. Well defined and recognized challenges in mask inspection and repair remain and the layout of alternating phase shifted masks present a design and data preparation overhead, but the data presented here demonstrate the feasibility of designing and building manufacturing quality alternating phase shifted masks for the gate level of a microprocessor.

Improving yield through the application of process window OPC

As the industry progresses toward more challenging patterning nodes with tighter error budgets and weaker process windows, it is becoming clear that current single process condition Optical Proximity Corrections (OPC) as well as OPC verification methods such as Optical Rules Checking (ORC) performed at a single process point fail to provide robust solutions through process. Moreover, these techniques can potentially miss catastrophic failures that will negatively impact yield while surely failing to capitalize on every chance to enhance process window. Process-aware OPC and verification algorithms have been developed [1,2] that minimize process variability to enhance yield and assess process robustness, respectively. In this paper we demonstrate the importance of process aware OPC and ORC tools to enable first time right manufacturing solutions, even for technology nodes prior to 45nm such as a 65nm contact level, by identifying critical spots on the layout that became significant yield detractors on the chip but nominal ORC could not catch. Similarly, we will demonstrate the successful application of a process window OPC (PWOPC) algorithm capable of recognizing and correcting for process window systematic variations that threaten the overall RET performance, while maintaining printed contours within the minimum overlay tolerances. Direct comparison of wafer results are presented for two 65nm CA masks, one where conventional nominal OPC was applied and a second one processed with PWOPC. Thorough wafer results will show how our process aware OPC algorithm was able to address and successfully strengthen the lithography performance of those areas in the layout previously identified by PWORC as sensitive to process variations, as well as of isolated and semi-isolated features, for an overall significant yield enhancement.

Optimizing style options for subresolution assist features

Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip line-width variation reduction when used in conjunction with modified illumination lithography. Work previously presented at this conference has focused on the optimization of sraf design rules that specify the predominantly one dimensional placement and width of assist features as a function of layout pitch. This paper will recount the optimization of SRAF style options that specify how SRAF are to behave in realistic two dimensional circuit layouts. Based on the work done to strike the correct balance between sraf manufacturability, CAD turnaround time, and lithographic benefit in IBMs early product implementation exercises, the evolution of sraf style options is presented. Using simulation as well as exposure data, this paper explores the effect of various two dimensional sraf layout solutions and demonstrates the use of model based verification in the optimization of sraf style options.

Methodology for balancing design and process tradeoffs for deep-subwavelength technologies

For process development of deep-subwavelength technologies, it has become accepted practice to use model-based simulation to predict systematic and parametric failures. Increasingly, these techniques are being used by designers to ensure layout manufacturability, as an alternative to, or complement to, restrictive design rules. The benefit of model-based simulation tools in the design environment is that manufacturability problems are addressed in a design-aware way by making appropriate trade-offs, e.g., between overall chip density and manufacturing cost and yield. The paper shows how library elements and the full ASIC design flow benefit from eliminating hot spots and improving design robustness early in the design cycle. It demonstrates a path to yield optimization and first time right designs implemented in leading edge technologies. The approach described herein identifies those areas in the design that could benefit from being fixed early, leading to design updates and avoiding later design churn by careful selection of design sensitivities. This paper shows how to achieve this goal by using simulation tools incorporating various models from sparse to rigorously physical, pattern detection and pattern matching, checking and validating failure thresholds.

SMO Photomask Inspection in the Lithographic Plane

Source Mask Optimization (SMO) describes the co-optimization of the illumination source and mask pattern in the frequency domain. While some restrictions for manufacturable sources and masks are included in the process, the resulting photomasks do not resemble the initial designs. Some common features of SMO masks are that the line edges are heavily fragmented, the minimum design features are small and there is no one-to-one correspondence between design and mask features. When it is not possible to link a single mask feature directly to its resist counterpart, traditional concepts of mask defects no longer apply and photomask inspection emerges as a significant challenge. Aerial Plane Inspection (API) is a lithographic inspection mode that moves the detection of defects to the lithographic plane. They can be deployed to study the lithographic impact of SMO mask defects. This paper briefly reviews SMO and the lithography inspection technologies and explores their applicability to 22nm designs by presenting SMO mask inspection results. These results are compared to simulated wafer print expectations.

Improvement of optical proximity-effect correction model accuracy by hybrid optical proximity-effect correction modeling and shrink correction technique for 10-nm node process

Abstract. The model accuracy of optical proximity-effect correction (OPC) was investigated by two modeling methods for a 10-nm node process. The first method is to use contours of two-dimensional structures extracted from critical dimension-scanning electron microscope (CD-SEM) images combined with conventional CDs of one-dimensional structures. The accuracy of this hybrid OPC model was compared with that of a conventional OPC model, which was created with only CD data, in terms of root-mean-square (RMS) error for metal and contact layers of 10-nm node logic devices. Results showed improvement of model accuracy with the use of hybrid OPC modeling by 23% for contact layer and 18% for metal layer, respectively. The second method is to apply a correction technique for resist shrinkage caused by CD-SEM measurement to extracted contours for improving OPC model accuracy. The accuracy of OPC model with shrink correction was compared with that without shrink correction, and total RMS error was decreased by 12% by using the shrink correction technique. It can be concluded that the use of CD-SEM contours and the shrink correction of contours are effective to improve the accuracy of OPC model for the 10-nm node process.

Yield optimization for third party library elements

Optimization of semiconductor product yield requires control of systematic defects. A variety of industry tools are available to check designs for systematic layouts that will be difficult to manufacture. Because of the cost associated with setting up the rules for a checking tool and the cost of licenses needed to evaluate designs, manufacturing process lines typically enable a limited set of tools to evaluate designs for systematic yield sensitivity. Semiconductor product design systems typically incorporate library elements designed by third party design companies. When third party library suppliers do not have access to the licenses or expertise to use the tools selected by the target manufacturing line, a barrier is created to having all library elements in a semiconductor design system checked to the same level. This results in a yield exposure for library elements that are not evaluated and fixed. This paper describes a method used to enable systematic yield evaluation for 32nm library elements procured from third party library suppliers. The third party library supplier provides layout data to the contracting library owner for yield sensitivity analysis. Changes are prioritized and fed back to the third party library supplier. This method interlocks design practices with the third party library supplier and provides a means for the contracting library owner to evaluate third party library elements and provide feedback to optimize the design.

Real-time VT5 model coverage calculations during OPC simulations

For a robust OPC solution, it is important to isolate and characterize the detractors from high quality printability. Failure in correctly rendering the design intent in silicon can have multiple causes. Model inability in predicting lithographic and process implications is one of them. Process model accuracy is highly dependant on the quality of data used in the calibration phase of the model. Structures encountered during the OPC simulation that have not been included in the calibration patterns, or even structures somewhat similar to those used in calibration, are some times incorrectly predicted. In this paper a new method for studying VT5 model coverage during OPC simulations is investigated. The aerial image parameters for a large number of test structures used for model calibration are first calculated. A novel sorting and data indexing algorithm is then applied to classify the computed data into fast accessible look-up tables. These tables are loaded in the beginning of a new OPC simulation where they are used as a reference for comparing aerial image parameters calculated for new design fragments. Such new approach enables real time classification of design fragments based on how well covered they are by the VT5 model. Employing this method avoids catastrophic misses in the correction phase and allows for a robust approach to MBOPC.

Image fidelity verification: contourIFV

The rapidly escalating complexity of resolution enhancement techniques (RET), now commonplace in leading edge lithography, requires accurate verification to avoid yield and performance problems on the patterned wafers. Model-based verification techniques that have been derived from optical proximity correction (OPC) obtain the required checking speed from sparse sampling of the layout at discrete evaluation points along the edges of layout patterns. This sparse sampling allows accurately calibrated models to be used for full chip checking applications. However, there is a demonstrated risk of missing significant patterning errors due to the sparse and edge-centric sampling of the layout. Grid-based simulation approaches which calculate the image on a fine grid over the entire layout space accurately detect patterning problems anywhere in the layout, but can be executed at reasonable runtimes for aerial image models only. The challenge for full-chip model-based verification of RET-enhanced layouts is, therefore, a trade-off between sparse, edge-centric simulation using accurate models versus simulations using approximate models over the entire layout space. This paper presents an approach, termed contourIFV, that has been demonstrated to overcome the aforementioned problems and has been shown to provide significant value in the verification of the RET and OPC prescription.