Jair Garcia-Lamont

A Digital Real Time Image Demosaicking Implementation for High Definition Video Cameras

This paper describes a digital real time image demosacking implementation for high definition video cameras. It comprises one buffer for three pixel rows and one interpolator based on bilinear interpolation. It has been implemented with HDL-Verilog and mapped onto Virtex-4 XC4VLX25 from Xilinx; for a clock frequency of 150 MHZ, its throughput is 72 frames per second. This implementation may be used as an intellectual property for FPGAs or SoC.

Implementation of Different Wavelets in an Auto-Tuning Wavenet PID Controller and Its Application to a DC Motor

This paper shows the results obtained experimentally by controlling the speed of a DC motor using different wavelets (Morlet, RASP1, RASP2, RASP3, POLYWOG1, POLYWOG3, POLYWOG4 and Shannon) in an auto-tuning wavenet PID controller. Such controller tunes online the proportional, integral and derivative gains of a classical discrete PID controller, through the identification of the plant using a radial basis neural network with different daughters wavelet activation functions, in cascade with an infinite impulse response filter.

Performance evaluation of an architecture for the characterisation of photo-devices: design, fabrication and test on a CMOS technology

In this report, the performance of a particular pixels architecture is evaluated. It consists mainly of an optical sensor coupled to an amplifier. The circuit contains photoreceptors such as phototransistors and photodiodes. The circuit integrates two main blocks: (a) the pixel architecture, containing four p-channel transistors and a photoreceptor, and (b) a current source for biasing the signal conditioning amplifier. The generated photocurrent is integrated through the gate capacitance of the input p-channel MOS transistor, then converted to voltage and amplified. Both input transistor and current source are implemented as a voltage amplifier having variable gain (between 10dB and 32dB). Considering characterisation purposes, this last fact is relevant since it gives a degree of freedom to the measurement of different kinds of photo-devices and is not limited to either a single operating point of the circuit or one kind and size of photo-sensor. The gain of the amplifier can be adjusted with an external DC power supply that also sets the DC quiescent point of the circuit. Design of the row-select transistors aspect ratio used in the matrix array is critical for the pixels amplifier performance. Based on circuit design data such as capacitance magnitude, time and voltage integration, and amplifier gain, characterisation of all the architecture can be readily carried out and evaluated. For the specific technology used in this work, the spectral response of photo-sensors reveals performance differences between phototransistors and photodiodes. Good approximation between simulation and measurement was obtained.

CMOS Vision Chip for Laser Spot Position Detection

This paper presents a vision chip for laser spot detection. The sensor has an architecture that comprises a 64x64 pixel array with a pixel pitch of 38.6μm x 30.8μm and fill factor of 30% and two position processors that deliver coordinate position for both axes. Under maximum speed condition, power consumption was 103mW, where maximum frame rate was 870000 frames per second. The maximum mismatch between pixels was 3% and maximum position accuracy was 0.013(2 x).

Performance simulation of retinal partial operations in “on” - and “off” -centers

The object the present work is to present a model for a retinal prosthesis. The translation of an algorithm on the standard technology of silicon sets a trade off between accurate of model and feasibility to implementation. That is, a high accurately of the model, normally results in more complexity, and therefore minus feasibly its implementation in hardware. To develop the model was necessary to review the receptive field concept, its classification and retinal architecture. The model consists in to reproduce the signal in a ganglion cell. This model has the advantage that is very simple with a high feasibly to implement on standard technology silicon. The mathematical representation comprises sustained and transient response which is the classification of the receptive fields. A second contribution of this work is the interpretation of the response of ganglion cell which will be analyzed along the developmental of this work. Simulations results are presented using the mathematical representation.

CMOS prototype for retinal prosthesis applications with analog processing

A core architecture for analog processing, which emulates a retina’s receptive field, is presented in this work. A model was partially implemented and built on CMOS standard technology through MOSIS. It considers that the receptive field is the basic unit for image processing in the visual system. That is why the design is concerned on a partial solution of receptive field properties in order to be adapted in the future as an aid to people with retinal diseases. A receptive field is represented by an array of 3×3 pixels. Each pixel carries out a process based on four main operations. This means that image processing is developed at pixel level. Operations involved are: (1) photo-transduction by photocurrent integration, (2) signal averaging from eight neighbouring pixels executed by a neu-NMOS (ν-NMOS) neuron, (3) signal average gradient between central pixel and the average value from the eight neighbouring pixels (this gradient is performed by a comparator) and finally (4) a pulse generator. Each one of these operations gives place to circuital blocks which were built on 0.5 μm CMOS technology.

CMOS prototype image sensor with edge enhancement to compensate for blurring

In this article, the design and realisation of an analogue complementary metal oxide semiconductor (CMOS) prototype image sensor with edge enhancement to compensate for blurring is presented. The chip is designed with voltage and current modes, and the main parts are one 16u2009×u200916 pixel array, one pair of absolute value circuits and three trans-impedance amplifiers. The technology process is TSMC 0.35u2009µm. The edge processing is performed in parallel on pixel level. The performance of the sensor comprises a processing time of 450u2009ns; an optical dynamic range of 53u2009dB; a power consumption, at 30 frames/s, of 1.5u2009mW; and a peak signal-to-noise ratio of 44u2009dB.

Electronic architecture for an analog retinal processing prototype suitable to be implemented on standard CMOS technology

An analog architecture of optic signal processing is presented in this work, with the goal to emulate one of the much processes involved in a biological retina. Here we have considered that the receptive field is the main unit of processing in the visual system. So, the proposed architecture tries to give partial solution to the properties of a receptive field in order to give some help to people with retinal diseases in the future. A receptive field is represented by an array of 3×3 pixels and four main mathematical operations are carried out on each one pixel. This means that image processing is developed at pixel level. Operations involved are: (1) photo-transduction by photocurrent integration; (2) Average of the signals coming from the eight neighbouring pixels, obtained by a neu-NMOS (v-NMOS) neuron; (3) The gradient between central pixel and the average value from neighboring pixels. This operation is done by a comparator; (4) a generator of impulses whose density is proportional to the gradient. The coupling methodology among every block or module, and the PSPICE simulation using the technology parameters of 0.5µm are the main objectives in this work.

Optical characterization of integrated P+/N-Well/P-substrate and N-Well/P-substrate photo-device structures on CMOS technology

Here, a characterization methodology for integrated silicon-based photo-devices is presented. Devices are phototransistors (“P+/N-Well/P-substrate”) and photodiodes (“N-Well/P-substrate”) with similar sizes, (9µm×9µm). They were integrated in a 1.5µm CMOS technology through MOSIS. Through these characterizations it is possible also to find out in general, the performance advantages and disadvantages, comparing measurements made on these kinds of structures. It was found that phototransistors have a better performance compared with photodiodes. The contribution from substrate leakage current in N-Well/P-substrate structures is high, as well as from carriers generated in the neighborhood of the pixel circuit. It is shown that crosstalk is the phenomenon that deviates the measured photo-response from the ideal model of photo-devices.

CMOS Digital Pixel for Binary Morphological Edge Segmentation

A digital pixel for binary morphological image processing is presented. The pixel is designed to be integrated into a vision chip with parallel architecture, in order to compute edge segmentation. The pixel contains 11 transistors working with analog signal and 20 transistor working with digital signal; pixel layout size is 115.2 mum times 89.4 mum; fill factor is 1.85%; 1.2 mum CMOS standard technology from AMI is used for prototyping; random noise is 2.7 mV; peak analog output signal to noise ratio is 44 dB; optical dynamic range is 53 dB; dark current is 11 mV/s; processing time is 3.5 ms; maximum power dissipation is 264 muW.