Mario Alfredo Reyes-Barranca

Study for the micromachining optimization of micro hotplates used in MEMS-CMOS gas sensors

Etching post-processes are usually done with systems based on MEMS structures compatible with CMOS technology like micro hotplates membranes used in MEMS gas sensors. Silicon anisotsropic etch steps follows fabrication of the integrated circuit in a silicon foundry for the release of the membrane but care should be taken to avoid damage to other layers used for integrated circuit fabrication, as aluminum for example. Therefore, a short time micromachining process can relieve these concerns but also should proceed to obtain a well defined suspended structure. This work shows an analysis that takes advantage of the different etching rate depending on the crystalline planes of the silicon substrate, in order to propose a geometry that could help to meet the objectives mentioned. Different geometries and orientation are studied using TMAHW as the anisotropic etching solution. Experimental results confirm previous simulations from AnisE® regarding the etching trend of four geometries analyzed, as the final geometry reduced the etching time substantially, in the order of 20%. The strategy defined in this work can be extended to other designs and applications.

A prototype design for an accelerometer using a multiple floating-gate MOSFET as a transducer

In this work, a design for a high G sensor is proposed demonstrating a novel transduction technique that can be fabricated with a standard 0.5μm CMOS technology. No additional modifications to the fabrication steps are needed to achieve a MEMS (Micro-Electro-Mechanical System) accelerometer. The proposed system uses Multiple Input Floating-gate MOS transistors (MIFGMOS) as capacitive transduction elements. A variable capacitance is configured between fingers attached to the proof mass as one plate, and to the fixed structure, as the other plate. When acceleration is applied, this results in a modification of the floating gate voltage of the FGMOS, with a corresponding current change that can be correlated to acceleration. Also, a mechanical study was made with a given geometry structure, as well as an electrical analysis of the FGMOS transistor performance. Finally, a layout is proposed for the accelerometer system. Therefore, it is demonstrated that this design can be fabricated with the desired specifications through a standard CMOS technology. Additionally a novel transduction alternative compared to that used in conventional designs is demonstrated.

Methodology for the design of a 4-bit soft-hardware-logic circuit based on neuron MOS transistors

As soft-hardware-logic circuits had been proposed in the literature as an alternative for digital circuits taking advantage the fact that any Boolean function could be implemented with the same cell, just configuring external signals, this work shows a methodology that could be followed particularly for the design of a four bits logic gate, using the so-called neuron MOS transistor (ν-MOS). Simulation results show the feasibility of the design for performing as XNOR, NOR, OR, XOR, AND or NAND logic gates, for instance. In order to extrapolate the design to a higher number of bits, the key issue is to properly consider the weight of the input capacitances in correlation with the number of input bits. A D/A converter can be used as the input stage of the configuration. This design considers the D/A converter-less version, since it helps to increase device integration as the number of transistors used is reduced with no difference in its performance. The design should be based on the theoretical floating potential diagram (FPD) of the desired logic gate.

Modal analysis of a structure used as a capacitive MEMS accelerometer sensor

In this paper a modal analysis for a proposed capacitive MEMS accelerometer sensor that can be used as inclinometer, dynamic acceleration or vibration sensor, is shown. An analysis of the effect of frequency over the displacement of the movable electrode is made. Besides, it is shown that the natural frequencies and vibration modes depend on the application given to this capacitive sensor. Additionally, the structure here proposed can be manufactured using standard CMOS technology. This paper shows how the same capacitive structure can be used in a MEMS sensor no matter what type of application you will provide. A model of the accelerometer is presented. The simulations shown were obtained using COMSOL.

MEMS capacitive sensor using FGMOS

In this paper, a capacitance structure configured with two plates to be used as a MEMS-sensor is presented. This capacitor was designed primarily for being used in combination with a floating-gate MOS transistor (FGMOS) as the transducer device of an accelerometer. One of the plates of this capacitance structure is fixed and the other plate will move when a force is applied, causing a variable capacitance, this is achieved by a lateral comb configuration. This variable capacitance depends either on the mechanical properties of the material used in the structure, the undesired displacement caused by gravity and pull-in effect. Furthermore, the proposed design can be fabricated using standard CMOS technologies followed by a sacrificial layer etching needed for the structure release.

3-layered capacitive structure design for MEMS inertial sensing

In this paper a two-terminal capacitive structure is presented in which a novel architecture with a double interleaved (interdigitated) scheme is introduced. This structure was originally conceived as a mechanism to achieve a greater capacitance between the plates (terminals) of an integrated capacitor using a relatively smaller design area in the standard 0.5μm, two polysilicon and three metal layers (2P3M) CMOS technology. This work presents the design and theoretical analysis of a three-metal interleaved structure used as a varactor tied down to the proof mass of an integrated CMOS-MEMS accelerometer where the active devices are floating-gate transistors (FGMOS) with a variable capacitive coupling coefficient. Nevertheless, the three-layered geometrical scheme may have a wide range of applications across the MEMS technology.

An adaptive geometrically-complemented approach for ECG signal denoising

This paper proposes a geometrical criterion for denoising a single-lead ECG signal. It was designed to ease the use of heuristic procedures for removing the most common types of noises from ANSI/AAMI-compliant ECG signals. However, in this paper, only the system-noise was considered to illustrate how this geometrical criterion is applied to the signal. The proposal here presented relies on a voltage-level slope detector that marks where the signal starts to increase, decrease or remain at the same level in order to perform an abstract segmentation of the ECG signal. The resulting segments are quantitatively classified as significant segments or noisy segments by analyzing their amplitude and time duration according to a previously defined threshold-level with the intention of helping the algorithm to decide its own operational parameters. The system-noise filter proposed here has five different operation modes. The main one is based on the arithmetic mean operation to smooth out short-term fluctuations; additionally, it is complemented with geometrical estimations for preserving the physiological characteristics of the ECG signal. The other operation modes are purely based on geometric estimations to calculate the filter output. The geometrical criterion described here differs from many other approaches presented until now owing to its low mathematical complexity and low computational consumption since all calculations can be performed with raw ADC readings and arithmetical operations, characteristics that make this filter easy to implement on embedded systems. This denoising approach was designed for online processing applications but it also works well with previously recorded signals.

A simple method for determination of Fowler–Nordheim tunnelling parameters

A simple technique for extracting the Fowler–Nordheim (FN) tunnelling parameters is proposed. It consists of measuring the Drain-Source current of a floating gate transistor while a linear ramp voltage is applied to a simple injector structure attached to the transistors floating gate. Such a test device is fabricated using a standard CMOS process. The parameters obtained can be used in a freely available electrical simulator as SPICE3f5 (NGSPICE), but in general it can be easily adapted to other SPICE-like programs. We describe the technique step-by-step and a comparison is made of simulated and measured FN tunnelling parameters, for a floating gate transistor with tunnelling injectors. A good agreement has been found between experimental and simulated data.

Performance simulation of retinal partial operations in “on” - and “off” -centers

The object the present work is to present a model for a retinal prosthesis. The translation of an algorithm on the standard technology of silicon sets a trade off between accurate of model and feasibility to implementation. That is, a high accurately of the model, normally results in more complexity, and therefore minus feasibly its implementation in hardware. To develop the model was necessary to review the receptive field concept, its classification and retinal architecture. The model consists in to reproduce the signal in a ganglion cell. This model has the advantage that is very simple with a high feasibly to implement on standard technology silicon. The mathematical representation comprises sustained and transient response which is the classification of the receptive fields. A second contribution of this work is the interpretation of the response of ganglion cell which will be analyzed along the developmental of this work. Simulations results are presented using the mathematical representation.

Time-multiplexing cellular neural network in FPGA for image processing

While efficient simulators for Time-Multiplexing Cellular Neural Networks have been reported, no reports on implementations in FPGA have been presented. A Time-Multiplexing Cellular Neural Network is implemented within a FPGA for image processing. The network has been used to perform tasks, such as edge detection and noise remover over several test templates. Implementation results are compared with a simulator using MATLAB and presented in this work showing that this procedure is very reliable for image processing.