Jose A. Moreno-Cadenas
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Featured researches published by Jose A. Moreno-Cadenas.
Sensors | 2010
Mario Alfredo Reyes Barranca; Salvador Mendoza-Acevedo; Luis M. Flores-Nava; Alejandro Ávila-García; Edgar Norman Vázquez-Acosta; Jose A. Moreno-Cadenas; Gaspar Casados-Cruz
Floating-gate MOS transistors have been widely used in diverse analog and digital applications. One of these is as a charge sensitive device in sensors for pH measurement in solutions or using gates with metals like Pd or Pt for hydrogen sensing. Efforts are being made to monolithically integrate sensors together with controlling and signal processing electronics using standard technologies. This can be achieved with the demonstrated compatibility between available CMOS technology and MEMS technology. In this paper an in-depth analysis is done regarding the reliability of floating-gate MOS transistors when charge produced by a chemical reaction between metallic oxide thin films with either reducing or oxidizing gases is present. These chemical reactions need temperatures around 200 °C or higher to take place, so thermal insulation of the sensing area must be assured for appropriate operation of the electronics at room temperature. The operation principle of the proposal here presented is confirmed by connecting the gate of a conventional MOS transistor in series with a Fe2O3 layer. It is shown that an electrochemical potential is present on the ferrite layer when reacting with propane.
International Journal of Electronics | 2009
A. S. Medina-Vazquez; Jesús de la Cruz-Alejo; Felipe Gomez-Castañeda; Jose A. Moreno-Cadenas
The aim of this article is to probe the advantages that the Multi-Input Floating Gate MOS (MIFGMOS) transistor has versus the conventional MOSFET transistor in order to design analogue circuits with low-voltage operation and good linearity. To show this, the design and implementation of both a voltage to current converter (VIC) cell and a memory current cell (MIC) using MIFGMOS transistors is presented. The development is based on mathematical and simulation analysis as well as experimental results. Both cells present good performance and linearity according to theoretical analysis with a supply voltage of 1.7 V and a power consumption of about 20 μW, despite the long channel technology. These characteristics could be very important in analogue and mixed signal applications requiring low supply voltage and low power consumption. The cells presented here can be part of a sample and hold circuit operating in current mode, but applications are not restricted. Additionally, a comparison between simulation and experimental results obtained when we tested five 3-input MIFGMOS transistors are included to show their properties and behavior.
international conference on electrical engineering, computing science and automatic control | 2013
Gerardo Marcos Tornez-Xavier; Felipe Gomez-Castañeda; Jose A. Moreno-Cadenas; Luis M. Flores-Nava
This work describes the development and FPGA implementation of a solar panel emulator. First we created the electric analog model of the solar panel using the Mentor Graphics framework, using the irradiance and temperature variables of a meteorological database as input signals and then obtaining the short circuit current and the open circuit voltage parameters to finally train an artificial neural network using Matlab, to perform the modeling of the response of the solar panel. Once the neural network was optimized, this was described in VHDL to simulate its response, to finally make its implementation in FPGA digital device and to be able to compare these results with those of a commercial solar panel.
international conference on electrical engineering, computing science and automatic control | 2014
Alvaro Narciso Perez-Garcia; Gerardo Marcos Tornez-Xavier; Luis M. Flores-Nava; Felipe Gomez-Castañeda; Jose A. Moreno-Cadenas
In this manuscript we present the implementation of an artificial neural network type Multilayer Perceptron (ANN-MP or NNMP) in Field-Programmable Gate Arrays (FPGA), including Back-Propagation training method based on descendent gradient. This network has 2 reconfigurable hidden layers, adjustable parameters (epochs and ratio learning) and batch learning. The proposed architecture aims to reduce the number of logical elements to be used, so serial processing is utilized. In order to test the performance of the trained network, a nonlinear function was approximated with satisfactory results.
international conference on electrical engineering, computing science and automatic control | 2014
Felipe Gomez-Castañeda; Gerardo Marcos Tornez-Xavier; Luis M. Flores-Nava; Oliverio Arellano-Cárdenas; Jose A. Moreno-Cadenas
In this manuscript we present the implementation in FPGA of ANFIS system (Adaptive Network-based Fuzzy Inference Systems) for a two-input architecture with three membership functions per input and nine fuzzy rules, used to set up a photovoltaic panel emulator. The starting point is the photovoltaic panel electric analog model simulated with ELDO, a tool of Mentor Graphics Suite, having as inputs irradiation and temperature from a meteorological data base so we can obtain the short-circuit current (Isc) and open circuit voltage (Voc) of the panel. With this information, ANFIS was trained within Matlab environment to approximate the photovoltaic panel response. The training was carried out for both, current and voltage, independently, and once achieved minimum error parameters, they were downloaded into the FPGA implemented architecture in order to assess its performance.
signal processing systems | 2007
Jesus E. Molinar-Solis; Felipe Gomez-Castañeda; Jose A. Moreno-Cadenas; Victor H. Ponce-Ponce
At present, the Cellular Neural Network (CNN) is a potential parallel structure able to perform image processing tasks in real-time when is effectively implemented in CMOS technology. The CNN silicon integration success is due mainly to the local connectivity of processing cells. In this work, an alternative design based on floating-gate MOS inverters is presented, which uses unipolar signals for solving binary tasks. The approach brings a fast response in a reduced silicon area, as shown through electrical simulations. A prototype cell in CMOS technology (AMI, 1.2 micron) was fabricated and tested for eight image processing tasks.
international symposium on circuits and systems | 2000
O. Arellano-Cardenas; H. Molina-Lozano; Jose A. Moreno-Cadenas; Felipe Gomez-Castañeda; Luis M. Flores-Nava
The architecture called ANFIS (Adaptive Neuro-Fuzzy Inference System) proposed by J.R. Jang (1993) is divided in five layers. Layers 1 and 2 in ANFIS were built by using a double-differential amplifier and a winner takes all circuit; to implement layers 3, 4 and 5, CMOS translinear blocks are used. The complete ANFIS architecture is implemented on a circuit board, using two CMOS circuits (N-well and 2 /spl mu/m minimum dimensions). The total system has two inputs with three membership functions each one, which generate a fuzzy space with nine subspaces and one single output. The system is used for classification of electrical signals.
international conference on electrical engineering, computing science and automatic control | 2010
L. Noé Oliva-Moreno; Jesús de la Cruz-Alejo; Jose A. Moreno-Cadenas
This work presents an optimized Implementation on Field Programmable Gate Array (FPGA) Architecture for an Infomax algorithm based on Independent Component Analysis (ICA). We use this algorithm to solving Blind Source Separation (BSS) problems in real-time mixed signal processing in order to clean speech signals under noisy environments and to probe the potential of this kind of algorithms embedded in hardware architectures. The work shows a new digital architecture of neural network composed by two dimensional arrays, the output signals present successful results according to theorical analysis and achieving the signals separation.
international conference on electrical and electronics engineering | 2007
J. de la Cruz-Alejo; F. Gomez-Castafieda; Jose A. Moreno-Cadenas; J.C. Iglesias-Rojas
This paper presents the performance of optimal filtering; LMS with a nonvolatile analog memory cell fabricated through 1.2um CMOS process, for the adaptive identification signal problem, where transfer functions are unknown and changing. The memory stores the weight in the filter as charge on the floating gate of a transistor pMOS. The update is linear, using a pulse density modulation scheme by means of tunneling and injection mechanisms. The LMS algorithm is implemented digitally off chip, and it does not require the signal to be piecewise stationary, and requires no manual operation other than selection of the step-size.
international conference on electrical and electronics engineering | 2006
L. N. Oliva-moreno; Jose A. Moreno-Cadenas; Luis M. Flores-Nava; Felipe Gomez-Castañeda
In this paper we use a digital signal processing unit (DSP) to implement an extended Infomax independent component analysis (ICA) algorithm for blind source separation (BSS). In this work we are going to reproduce the performance of the net implementation as expected in Matlab. A first hardware implementation has been designed and the experimental results are presented. In the developed experiments we used recorded signals and then they were processed in the DSP unit in real-time. The performance comparison are made with 2times2 net