Wolfgang Pribyl

CMOS output buffers for megabit DRAMs

Output buffers for CMOS DRAMs are discussed and associated reliability risks and circuit design problems are shown. Concepts using true CMOS circuitry for output buffers are presented. Measurement results prove the feasibility of latch-up-free CMOS output structures, which have been implemented on a 4-Mb DRAM and use significantly less area than boosted NMOS concepts. >

Critical charge model for transient latch-up in VLSI CMOS circuits

Experimental results and theoretical considerations on the critical charge model for latch-up in VLSI CMOS circuits are presented. The critical charge is constant, proportional to the trigger phase pulse height, and inversely proportional to the trigger pulse width. With these results it is possible to calculate the transient latch-up susceptibility of circuits due to periodic pulses, e.g. overshoot, undershoot, and glitches.<<ETX>>

Ein 4-Megabit dynamischer Speicher in Sub-μm-CMOS-Technologie

Seit im Jahre 1970 der erste 1 kBit dynamische Speicher (DRAM) am Markt verfugbar wurde, steigerte sich in regel masiger Folge die Integrations- und somit Speicherdichte. Derzeit befindet sich mit dem 4-Megabit Speicher die siebente Generation dynamischer Halbleiterspeicher in Entwicklung, der Fertigungsanlauf dieser Generation kann bei fuhrenden Herstellern fur das Jahr 1989 erwartet werden.