James B. Burr

Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS

An 80,000 transistor, low swing, 32~x~32-bit multiplier was fabricated in a standard 0.35μm,<italic>V</italic><subscrpt>th</subscrpt>=0.5 V CMOS process and in a 0.35μm, back-bias tunable, near-zero <italic>V</italic><subscrpt>th</subscrpt> process. While standard CMOS at<italic>V</italic><subscrpt>dd</subscrpt>=3.3 V runs at 136 MHz, the same performance can be achieved in the low- <italic>V</italic><subscrpt>th</subscrpt> version at <italic>V</italic><subscrpt>dd</subscrpt>=1.3 V, resulting in more than 5 times lower power. Similar power reductions are obtained for frequencies down to 10 MHz. In addition, the low-<italic>V</italic><subscrpt>th</subscrpt> version is able to run at 188 MHz, which is 38% faster than standard CMOS.

Energy-efficient 32/spl times/32-bit multiplier in tunable near-zero threshold CMOS

An 80,000 transistor, low swing, 32/spl times/32-bit multiplier was fabricated in a standard 0.35 /spl mu/m, V/sub th/=0.5 V CMOS process and in a 0.35 /spl mu/m, back-bias tunable, near-zero V/sub th/ process. While standard CMOS at V/sub dd/=3.3 V runs at 136 MHz, the same performance can be achieved in the low-V/sub th/ version at V/sub dd/=1.3 V, resulting in more than 5 times lower power. Similar power reductions are obtained for frequencies down to 10 MHz. In addition, the low-V/sub th/ version is able to run at 188 MHz, which is 38% faster than standard CMOS.