Masataka Matsui

200 MHz video compression macrocells using low-swing differential logic

Improving the performance of fully dedicated macrocells is key to realizing HDTV-resolution video de/compression LSIs operating at more than 100 MHz, having reasonable power consumption and chip size small enough for consumer applications. Existing circuit techniques are either not sufficiently fast or are area consuming. However, these problems are overcome by using low-swing differential logic to realise such macrocells.<<ETX>>

A single-chip MPEG2 video decoder LSI

This MPEG2 video decoder LSI decodes MPEG2 standard bit streams. The compression algorithm in the MPEG2 is based on discrete cosine transform (DCT), variable length coding, and motion compensation similar to the MPEG1, the earlier standard. However, the processing speed should be more than four times faster than MPEG1. Moreover, several algorithms and structures to handle interlaced pictures are added to the MPEG1 standard. This LSI decodes in real time all motion-compensation modes and picture structures in MPEG2 bit streams of not only CCIR601 but also HDTV resolution.<<ETX>>

A single-chip MPEG-2 codec based on customizable media embedded processor

A single-chip MPEG-2 MP@ML codec, integrating 3.8M gates on a 72-mm/sup 2/ die, is described. The codec employs a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video and audio concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a very-long-instruction-word coprocessor, digital signal processor instructions, and hardware engines. Making full use of the extensions and optimizing the architecture of each microprocessor based upon the nature of specific tasks, the chip can execute not only MPEG-2 MP@ML video/audio/system encoding and decoding concurrently, but also MPEG-2 MP@HL decoding in real time.

A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines

A 128 K/spl times/8-b CMOS SRAM is described which achieves a 25-ns access time, less than 40-mA active current at 10 MHz, and 2-/spl mu/A standby current. The novel bit-line circuitry (loading-free bit line), using two kinds of NMOSFETs with different threshold voltages, improves bit-line signal speed and integrity. The two-stage local amplification technique minimizes the data-line delay. The dynamic double-word-line scheme (DDWL) allows the cell array to be divided into 32 sections along the word-line direction without a huge increase in chip area. This allows the DDWL scheme to reduce the core-area delay time and operating power to about half that of other conventional structures. A double-metal 0.8-/spl mu/m twin-tub CMOS technology has been developed to realize the 5.6/spl times/9.5-/spl mu//SUP 2/ cell size and the 6.86/spl times/15.37-mm/SUP 2/ chip size.

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz. >

An 8 ns 1 Mb ECL BiCMOS SRAM

A description is given of a 1-Mb*1ECL (emitter-coupled-logic) SRAM (static random access memory) fabricated with a 0.8- mu m BiCMOS technology which has 8-ns access time and is 10K-I/O (input/output) compatible. To achieve sub-10 ns address access time and low power consumption, an ECL CMOS level converter, a bit-line peripheral circuit, and an automatic power saving function are employed. Details of the 0.8- mu m BiCMOS process technology are summarized, and an oscilloscope photograph shows 8-ns address access time under nominal conditions. The RAM characteristics are summarized.<<ETX>>

A single-chip MPEG-2 codec based on customizable media microprocessor

A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on a 72mm/sup 2/ die, is described. It has a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video, audio etc. concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a VLIW one and a DSP one inherent in its architecture. Making full use of the extensions, the chip executes encoding and decoding of video, audio and system concurrently in real time.

Energy-efficient 32 × 32-bit multiplier in tunable near-zero threshold CMOS

An 80,000 transistor, low swing, 32~x~32-bit multiplier was fabricated in a standard 0.35μm,<italic>V</italic><subscrpt>th</subscrpt>=0.5 V CMOS process and in a 0.35μm, back-bias tunable, near-zero <italic>V</italic><subscrpt>th</subscrpt> process. While standard CMOS at<italic>V</italic><subscrpt>dd</subscrpt>=3.3 V runs at 136 MHz, the same performance can be achieved in the low- <italic>V</italic><subscrpt>th</subscrpt> version at <italic>V</italic><subscrpt>dd</subscrpt>=1.3 V, resulting in more than 5 times lower power. Similar power reductions are obtained for frequencies down to 10 MHz. In addition, the low-<italic>V</italic><subscrpt>th</subscrpt> version is able to run at 188 MHz, which is 38% faster than standard CMOS.

SRAM cell stability under the influence of parasitic resistances and data holding voltage as a stability prober

The reliability and performance of SRAM are highly dependent on the cell stability, and the stability is affected by parasitic resistances in a memory array. The parasitic resistances result in a correlative behavior of the cells and are difficult to analyze and measure in a memory array. This topic has been rarely discussed in the literature. In this paper, the correlative behavior is analyzed by trajectories in a phase diagram composed by cell storage nodes. Electrical probing is done by the data holding test. The validity of the analysis and the probing method is confirmed by the measurements on a 0.8-/spl mu/m 1-Mb CMOS SRAM. An aspect of the cell scaling with attention to the parasitic resistance is also discussed.

Special memory and embedded memory macros in MPEG environment

Special memory and embedded memories used in a newly designed MPEG2 decoder LSI are described. Orthogonal memory is employed in a IDCT (Inverse Discrete Cosine Transform) block for small area and power. FIFOs and other dual-port memories are designed by using a single-port RAM operated twice in one clock cycle to reduce cost. As for testability, direct test mode is implemented for small area. An instruction RAM is placed outside the pad area in parallel to a normal instruction ROM and activated by Al-masterslice for extensive debugging and an early sampling. Other memory related techniques and the key features of the decoder are also described.