James C. Ellenbogen

Programmable nanowire circuits for nanoprocessors

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm2. The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input–output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Moletronics: future electronics

Abstract Over the past several years there have been dramatic advances toward the realization of electronic computers integrated on the molecular scale. First, individual molecules were demonstrated that serve as incomprehensibly tiny switches and wires one million times smaller than those on conventional silicon microchips 1 , 2 , 3 , 4 . This has resulted very recently in the assembly and demonstration of tiny computer logic circuits built from such molecular-scale devices 4 , 5 , 6 , 7 , 8 , 9 , 10 . A major force responsible for these revolutionary developments has been the molecular electronics or ‘Moletronics’ Program organized by the US Governments Defense Advanced Research Projects Agency (DARPA). Previously, DARPA gave birth to the Internet in the 1970s and 1980s, revolutionizing the way the world communicates. Now, the agency is setting its sights on a new revolution in the nature, structure, and scale of the very materials with which the world both computes and builds. Ultimately, to compute with molecular-scale structures — i.e. nanometer-scale structures — one must learn how to characterize and organize them on similar scales, one by one and in vast arrays. This is creating a whole new science and industry of ‘nanostructured materials’, such as are portrayed in Fig. 1 Download : Download high-res image (14KB) Download : Download full-size image Fig. 1 . Moletronics nanostructured materials. (a) Electron micrograph of self-assembled ErSi2 nanowires developed at HP. (Reproduced with permission from 54 .); (b) electron micrograph of cowpea viral particle modified with gold nanoclusters developed at NRL to use as a template for molecular self-assembly; (c) simulation of Rice Universitys gold-nanoparticle electrical contacts on a surface in a ‘NanoCell’ molecular logic structure 51 ; (d) structural diagram of NDR diode switch molecule 20 , 28 , 35 and a simulation of its molecular orbitals involved in switching. (Reproduced with permision from 47 . Copyright 2000 American Chemical Society.); (e) gold nanobars synthesized at PSU; (f) electron micrograph of nanowire transistor-based logic circuit 4 that was self-assembled and demonstrated at Harvard University.(Reprinted with permission from 5 . Copyright 2001 American Association for the Advancement of Science.) .

Nanowire nanocomputer as a finite-state machine.

Significance Fundamental limits soon may end the decades-long trend in microelectronic computer circuit miniaturization that has led to much technological and economic progress. Nanoelectronic circuits using new materials, devices, and/or fabrication methods face formidable challenges to provide alternatives for future microelectronics. A key advance toward overcoming these hurdles is achieved in this work through the construction of a nanoelectronic finite-state machine (nanoFSM) computer using “bottom–up” methods. The nanoFSM integrates both computing and memory elements, which are organized from individually addressable and functionally identical nanodevices, to perform clocked, multistage logic. Furthermore, the device density is the highest reported to date for any nanoelectronic system. Advances in logic and design in the nanoFSM are scalable and should enable more extensive nanocomputers. Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom–up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future.

Designs for Ultra-Tiny, Special-Purpose Nanoelectronic Circuits

Designs and simulation results are given for two small, special-purpose nanoelectronic circuits. The area of special-purpose nanoelectronics has not been given much consideration previously, though much effort has been devoted to the development of general-purpose nanoelectronic systems, i.e., nanocomputers. This paper demonstrates via simulation that the nanodevices and nanofabrication techniques developed recently for general-purpose nanocomputers also might be applied with substantial benefit to implement less complex nanocircuits targeted at specific applications. Nanocircuits considered here are a digital controller for the leg motion on an autonomous millimeter-scale robot and an analog nanocircuit for amplification of signals in a tiny optoelectronic sensor or receiver. Simulations of both nanocircuit designs show significant improvement over microelectronic designs in metrics such as footprint area and power consumption. These improvements are obtained from designs employing nanodevices and nanofabrication techniques that already have been demonstrated experimentally. Thus, the results presented here suggest that such improvements might be realized in the near term for important, special-purpose applications.

Scalability Simulations for Nanomemory Systems Integrated on the Molecular Scale

Abstract: Simulations were performed to assess the prospective performance of a 16 Kbit nanowire‐based electronic nanomemory system. Commercial off‐the‐shelf microcomputer system modeling software was applied to evaluate the operation of an ultra‐dense storage array. This array consists of demonstrated experimental non‐volatile nanowire diode switches, plus encoder‐decoder structures consisting of demonstrated experimental nanowire‐based nanotransistors, with nanowire interconnects among all the switching devices. The results of these simulations suggest that a nanomemory of this type can be operated successfully at a density of 1011 bits/cm2. Furthermore, modest device alterations and system design alternatives are suggested that might improve the performance and the scalability of the nanomemory array. These simulations represent early steps toward the development of a simulation‐based methodology to guide nanoelectronic system design in a manner analogous to the way such methodologies are used to guide microelectronic system design in the silicon industry.

Architectures and Simulations for Nanoprocessor Systems Integrated on the Molecular Scale

This chapter concerns the design, development, and simulation of nanoprocessor systems integrated on the molecular scale. It surveys ongoing re- search and development on nanoprocessor architectures and discusses challenges in the implementation of such systems. System simulation is used to identify some advantages, issues, and trade-offs in potential implementations. Previously, the au- thors and their collaborators considered in detail the requirements and likely per- formance of nanomemory systems. This chapter recapitulates the essential aspects of that earlier work and builds upon those efforts to examine the likely architectures and requirements of nanoprocessors. For nanoprocessor systems, simulation, as well as design and fabrication, embodies unique problems beyond those introduced by the large number of densely-packed, novel nanodevices. For example, unlike the largely homogeneous structure of circuitry in nanomemory arrays, a high degree of variety and inhomogeneity must be present in nanoprocessors. Also, issues of clocking, signal restoration, and power become much more significant. Thus, build- ing and operating nanoprocessor systems will present significant new challenges and require additional innovations in the application of molecular-scale devices and circuits, beyond those already achieved for nanomemories. New nanoelectronic de- vices, circuits, and architectures will be necessary to perform the more complex and specialized functions inherent in processing systems at the nanometer scale. This chapter highlights the fundamental design requirements of such nanoprocessor systems, presents various device and design options, and discusses their potential implications for system performance.