Shamik Das

Programmable nanowire circuits for nanoprocessors

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ∼960 μm2. The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input–output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.

Nanowire nanocomputer as a finite-state machine.

Significance Fundamental limits soon may end the decades-long trend in microelectronic computer circuit miniaturization that has led to much technological and economic progress. Nanoelectronic circuits using new materials, devices, and/or fabrication methods face formidable challenges to provide alternatives for future microelectronics. A key advance toward overcoming these hurdles is achieved in this work through the construction of a nanoelectronic finite-state machine (nanoFSM) computer using “bottom–up” methods. The nanoFSM integrates both computing and memory elements, which are organized from individually addressable and functionally identical nanodevices, to perform clocked, multistage logic. Furthermore, the device density is the highest reported to date for any nanoelectronic system. Advances in logic and design in the nanoFSM are scalable and should enable more extensive nanocomputers. Implementation of complex computer circuits assembled from the bottom up and integrated on the nanometer scale has long been a goal of electronics research. It requires a design and fabrication strategy that can address individual nanometer-scale electronic devices, while enabling large-scale assembly of those devices into highly organized, integrated computational circuits. We describe how such a strategy has led to the design, construction, and demonstration of a nanoelectronic finite-state machine. The system was fabricated using a design-oriented approach enabled by a deterministic, bottom–up assembly process that does not require individual nanowire registration. This methodology allowed construction of the nanoelectronic finite-state machine through modular design using a multitile architecture. Each tile/module consists of two interconnected crossbar nanowire arrays, with each cross-point consisting of a programmable nanowire transistor node. The nanoelectronic finite-state machine integrates 180 programmable nanowire transistor nodes in three tiles or six total crossbar arrays, and incorporates both sequential and arithmetic logic, with extensive intertile and intratile communication that exhibits rigorous input/output matching. Our system realizes the complete 2-bit logic flow and clocked control over state registration that are required for a finite-state machine or computer. The programmable multitile circuit was also reprogrammed to a functionally distinct 2-bit full adder with 32-set matched and complete logic output. These steps forward and the ability of our unique design-oriented deterministic methodology to yield more extensive multitile systems suggest that proposed general-purpose nanocomputers can be realized in the near future.

Designs for Ultra-Tiny, Special-Purpose Nanoelectronic Circuits

Designs and simulation results are given for two small, special-purpose nanoelectronic circuits. The area of special-purpose nanoelectronics has not been given much consideration previously, though much effort has been devoted to the development of general-purpose nanoelectronic systems, i.e., nanocomputers. This paper demonstrates via simulation that the nanodevices and nanofabrication techniques developed recently for general-purpose nanocomputers also might be applied with substantial benefit to implement less complex nanocircuits targeted at specific applications. Nanocircuits considered here are a digital controller for the leg motion on an autonomous millimeter-scale robot and an analog nanocircuit for amplification of signals in a tiny optoelectronic sensor or receiver. Simulations of both nanocircuit designs show significant improvement over microelectronic designs in metrics such as footprint area and power consumption. These improvements are obtained from designs employing nanodevices and nanofabrication techniques that already have been demonstrated experimentally. Thus, the results presented here suggest that such improvements might be realized in the near term for important, special-purpose applications.

Architectures and Simulations for Nanoprocessor Systems Integrated on the Molecular Scale

This chapter concerns the design, development, and simulation of nanoprocessor systems integrated on the molecular scale. It surveys ongoing re- search and development on nanoprocessor architectures and discusses challenges in the implementation of such systems. System simulation is used to identify some advantages, issues, and trade-offs in potential implementations. Previously, the au- thors and their collaborators considered in detail the requirements and likely per- formance of nanomemory systems. This chapter recapitulates the essential aspects of that earlier work and builds upon those efforts to examine the likely architectures and requirements of nanoprocessors. For nanoprocessor systems, simulation, as well as design and fabrication, embodies unique problems beyond those introduced by the large number of densely-packed, novel nanodevices. For example, unlike the largely homogeneous structure of circuitry in nanomemory arrays, a high degree of variety and inhomogeneity must be present in nanoprocessors. Also, issues of clocking, signal restoration, and power become much more significant. Thus, build- ing and operating nanoprocessor systems will present significant new challenges and require additional innovations in the application of molecular-scale devices and circuits, beyond those already achieved for nanomemories. New nanoelectronic de- vices, circuits, and architectures will be necessary to perform the more complex and specialized functions inherent in processing systems at the nanometer scale. This chapter highlights the fundamental design requirements of such nanoprocessor systems, presents various device and design options, and discusses their potential implications for system performance.

SPICE-compatible compact model for graphene field-effect transistors

This paper presents a compact device model for graphene field-effect transistors. This model extends prior iterative models (due to Meric et al. and Thiele et al.) in two ways. First, the model is given as a closed-form expression that is more computationally efficient. Second, it is valid for devices based upon either monolayer graphene or bilayer graphene. Simulations demonstrate that this model agrees closely with experimental data. Furthermore, the efficiency of this model enables the design and analysis of logic circuits composed of multiple graphene devices. Example simulation results are provided that demonstrate the potential for graphene-based circuit speeds five times that of circuits based upon 32-nm silicon technology.

Clocking nanocircuits for nanocomputers and other nanoelectronic systems

Prospective performance bounds are determined by simulation for a class of all-nanoelectronic clocking circuits. Such nano circuits could be utilized as on-chip master clocks for stand-alone nanosystems, as local clocks within nanoelectronic computers, or as local oscillators in mixed-signal nanoelectronic applications. Designs and simulation results are presented for these nano circuits, which are intended to be manufacturable using presently available nanodevices and nanofabrication techniques. The results presented here indicate that such clocking nano circuits, if built using presently available devices, could achieve operating frequencies up to approximately 1 GHz for analog applications and ISO MHz for digital nanoelectronic systems.

Static feedback circuit methodology for solving fixed-point equations

In this paper we consider the use of static analog VLSI circuits for iteratively maximizing cost functions that admit a fixed point recursion. We show through circuit simulation that certain classes of fixed point equations can be solved iteratively via the settling to steady state equilibrium of properly designed static-feedback CMOS circuits biased in the subthreshold region of operation. To demonstrate the power of this approach, we design a family of circuits to compute the right principal singular vector of arbitrarily sized positive real matrices by casting the singular vector extraction problem into a fixed point iterative map. We also illustrate the methodology more simply with a square root solver that uses the Babylonian fixed point equation. All circuits are current-mode translinear circuits with no extrinsic capacitors. This permits fast, low-power computation since the principal delay component is the settling time of the static circuits, and the few transistors required are biased in weak inversion.

Introduction to Special Issue: Highlights of NANOARCH'09

This special issue of the ACM Journal of Emerging Technologies in Computing Systems (JETC) presents key papers from the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’09). NANOARCH is the IEEE and ACM’s premier annual symposium devoted to the presentation and discussion of novel nanoelectronic system architectures. On 30–31 July 2009, the fifth of these symposia was convened in San Francisco, California, in partnership with the Design Automation Conference (DAC). Important challenges addressed at NANOARCH include the design challenges that will arise in computing with massive numbers of devices as well as the challenges arising from the complexity of managing defects and faults in such systems. The three articles in this special issue confront both sets of challenges. Two articles, by Dingler et al. and Gaillardon et al., respectively, present architectures for computing systems based on novel nanodevices and schemes for manufacturing at post-CMOS sublithographic scales. The third article, by Haron and Hamdioui, confronts reliability issues in ultra-dense nanomemory systems. In “Performance and Energy Impact of Locally Controlled NML Circuits,” Aaron Dingler, Michael Niemier, X. Sharon Hu, and Evan Lent evaluate the performance of a form of magnetic quantum-dot cellular automata known as Nanomagnet Logic (NML). Their evaluation is notable because it incorporates for the first time a detailed consideration of the performance impact of the magnetic clocking scheme that is required to drive NML. The authors find that, even with the overhead due to clocking, the energydelay product of NML 32-bit full adder circuits compares favorably with that of CMOS. Also, it could be improved even further through the use of new magnetic materials or higher-permeability cladding dielectrics. In “Matrix Nanodevice-Based Architectures and Associated Functional Mapping Method,” authors Pierre-Emmanuel Gaillardon, Ian O’Connor, Junchen Liu, Maimouna Amadou, Fabien Clermidy, and Gabriela Nicolescu present a novel nanoscale computing architecture based on the interconnection of fine-grained logic cells. The logic cells they consider are individual reconfigurable logic gates based on carbon nanotube transistors (CNTFETs). However, the authors point out that their approach generalizes to any matrix of ultra-fine reconfigurable cells. By mapping various benchmark circuits onto this architecture, Gaillardon et al. show that the architecture may provide up to a 14-fold improvement in functional density when compared with commercial silicon CMOS FPGAs. This occurs due to the great reduction in area provided by CNTFET-based logic cells, which is sufficient to overcome the increased interconnection overhead arising from the much finer-grained logic. In “Redundant Residue Number System Code for Fault Tolerance Hybrid Memories,” Nor Zaidi Haron and Said Hamdioui present a modified redundant residue number system (RRNS) coding scheme to enhance the reliability of nanomemory systems in the presence of transient and intermittent faults. By introducing this code, which uses fewer residues, the authors present a lower-overhead fault tolerance option with a correction capability near to that of conventional RRNS. This trade-off introduces the advantage of improved data storage capacity compared to RRNS, as well as ReedSolomon codes, due to a shorter codeword length. The authors also show that their modification improves the speed of RRNS decoding.