James C. Morizio

A wireless multi-channel recording system for freely behaving mice and rats.

To understand the neural basis of behavior, it is necessary to record brain activity in freely moving animals. Advances in implantable multi-electrode array technology have enabled researchers to record the activity of neuronal ensembles from multiple brain regions. The full potential of this approach is currently limited by reliance on cable tethers, with bundles of wires connecting the implanted electrodes to the data acquisition system while impeding the natural behavior of the animal. To overcome these limitations, here we introduce a multi-channel wireless headstage system designed for small animals such as rats and mice. A variety of single unit and local field potential signals were recorded from the dorsal striatum and substantia nigra in mice and the ventral striatum and prefrontal cortex simultaneously in rats. This wireless system could be interfaced with commercially available data acquisition systems, and the signals obtained were comparable in quality to those acquired using cable tethers. On account of its small size, light weight, and rechargeable battery, this wireless headstage system is suitable for studying the neural basis of natural behavior, eliminating the need for wires, commutators, and other limitations associated with traditional tethered recording systems.

Enhanced phase noise modeling of fractional-N frequency synthesizers

Mathematical models for the behavior of fractional-N phase-locked-loop frequency synthesizers (Frac-N) are presented. The models are intended for calculating rms phase error and determining spurs in the output of Frac-N. The models describe noise contributions due to the charge pump (CP), the phase frequency detector (PFD), the loop filter, the voltage control oscillator, and the delta-sigma modulator. Models are presented for the effects of static CP gain mismatch, CP dynamic mismatch and PFD reset delay mismatch. A simple analytic expression shows the level of /spl Delta//spl Sigma/ sequence noise caused by static CP current mismatch. We further show that un-equal rise time and fall time constants of the CP result in dynamic mismatch noise. Reset delay mismatch in PFD is shown to also contribute significantly to close-in phase noise. The model takes into account the reduction in CP thermal and flicker noise due to the changing duty cycle of Frac-N CP. Our model is therefore useful in characterizing the noise performance of Frac-N at the system-level, simplifying the design of fractional-N synthesizers and transmitters. Analytical and simulated results are compared and show good agreement with prior published data on Frac-N realizations.

A wirelessly controlled implantable LED system for deep brain optogenetic stimulation.

In recent years optogenetics has rapidly become an essential technique in neuroscience. Its temporal and spatial specificity, combined with efficacy in manipulating neuronal activity, are especially useful in studying the behavior of awake behaving animals. Conventional optogenetics, however, requires the use of lasers and optic fibers, which can place considerable restrictions on behavior. Here we combined a wirelessly controlled interface and small implantable light-emitting diode (LED) that allows flexible and precise placement of light source to illuminate any brain area. We tested this wireless LED system in vivo, in transgenic mice expressing channelrhodopsin-2 in striatonigral neurons expressing D1-like dopamine receptors. In all mice tested, we were able to elicit movements reliably. The frequency of twitches induced by high power stimulation is proportional to the frequency of stimulation. At lower power, contraversive turning was observed. Moreover, the implanted LED remains effective over 50 days after surgery, demonstrating the long-term stability of the light source. Our results show that the wireless LED system can be used to manipulate neural activity chronically in behaving mice without impeding natural movements.

P-25: A LCOS Microdisplay Driver with Frame Buffering Pixels

An 8-bit LCOS microdisplay driver for projection display has been designed and fabricated using AMI 0.5 um double-poly, triple-level metal CMOS process. The driver includes new frame buffer pixels which presents optimized optical characteristics for Field Sequential Color technique, and a mixed mode grayscale method which implements distinct 256 gray levels per color with a simple driver architecture. The voltage at the frame buffer pixels varies from 0 to 4.25 volts. The new frame buffer pixels enables a LCOS microdisplay to improve brightness without the loss of contrast ratio.

Wireless Headstage for Neural Prosthetics

The continuous monitoring of electrical brain activity with implanted electrodes is essential for understanding the neural substrates of many physiological and pathological brain functions. Although this is done in some patients before undergoing surgical treatment, such recordings are extremely difficult in experimental animals, particularly in small rodents. The wires from the implanted electrodes restrain and interfere with the natural behavior of the animals. Consequently, it has been impossible to correlate truly normal behavior with neuronal activity. In addition, it would be ideal if brain activity could be monitored while animals live in a natural and enriched environment. A neural prosthetic device is comprised of a hardware system that records neural activity from the brain and then decodes it into control signals that in turn can be used to move robotic devices or muscles. Todays neural prosthetic devices typically use tethered headstage connections that interface the brain headstage electronics to the remote spike sorting processors located at the controlled devices. In this paper we present the circuits, layouts and test data for a multi-channel wireless headstage system which includes the headstage transmitter and receiver components

Novel frame buffer pixel circuits for liquid-crystal-on-silicon microdisplays

A 32 /spl times/ 16 liquid-crystal-on-silicon (LCOS) backplane with novel frame buffer pixels is designed and fabricated using the AMI Semiconductors 0.5-/spl mu/m double-poly triple-metal CMOS process. The three novel pixel circuits described herein increase the brightness of an XGA LCOS microdisplay by at least 36% without sacrificing image contrast ratio. The increase of brightness is attributed to maximizing overall image view time, allowing an image to be displayed at full contrast while the next image is buffered onto the backplane. The new circuits achieve this by removing charge sharing and charge inducement problems shown in previously proposed frame buffer pixel circuits. Voltages on the pixel electrodes measured through rail-to-rail operational amplifiers with negative feedback vary from 0 to 4.25 V (6-V power source). All data voltage levels remain constant over a frame time with less than 1% drop, thus ensuring maximum contrast ratio. Modeling and experimental measurement on the fabricated chip show that these pixel circuits outperform all others to date based on storage time, data storage level, and potential for highest contrast ratio with maximum brightness.

64-channel ultrasound transducer amplifier

In this paper we present a 64-channel ultrasound preamplifier device that is used to amplify and filter pulsed echo transducer signals sourced from a real time three dimensional (RT3DU) non-invasive ultrasound system. Schematics, simulation data, and layout for each of the broadband sub-circuit macros are described which include a high gain preamplifier, a linear output buffer, and bias circuits. This device was implemented using AMI Semiconductors, 0.5 /spl mu/m, double poly, triple level metal CMOS technology. The device floorplan, circuit schematics and layout, specifications and measured test data are presented.

A multichannel CMOS analog front end IC for neural recordings

A multichannel integrated circuit for processing extracellular neural signals has been designed and manufactured. The analog CMOS IC consists of 17 parallel channels, each comprised of three cascaded stages: bandpass filter with gain, switched capacitor filters, and output buffer with selectable gain. The bandpass filter stage features an opamp with non-inverting resistor feedback and an off-chip capacitor in the feedback pathway to provide gain (43 dB) and one high pass filter pole (220 Hz). The low pass pole is set by the gain-bandwidth product of the opamp. In the switched capacitor filter stage, a one-pole high pass filter (500 Hz) cascades into a two-pole biquadratic low pass filter (5 kHz). The switched capacitor filters may be controlled by either an onboard tunable ring oscillator centered at 50 kHz or an off-chip clock. A four-phase clock splitter provides the necessary filter control-signals; a phase delay of 180/spl deg/ between the high and low pass clock lines maximizes settling time between the filters. The output buffer stage provides selectable gain at 20 dB or 32 dB. The IC was manufactured by AMI using a 0.5 /spl mu/m triple metal double poly process, and measures 4.2 /spl times/ 3.8 mm. The die is designed to be packaged in a flip-chip sub-assembly.

16-channel neural pre-conditioning device

We present the mixed-signal circuit design, layout, implementation techniques, and test data for a 16-channel neural pre-conditioning device that is used to amplify and filter signals acquired from chronically implanted electrodes in an animals brain. Schematics and simulation data for each of the subcircuit macros are presented which include a high gain, continuous time first order bandpass filter pre-amplifier, a cascaded bandpass switch capacitor filter, a selectable gain output buffer, and a voltage controlled oscillator based clock generation circuitry. This device was implemented using AMIs, 0.5 /spl mu/m, double poly, triple level metal, 5 V, CMOS technology. The layout and floorplan, specifications and test data for this device conclude this paper.

A LCOS microdisplay driver with frame buffer pixels

An 8-bit liquid crystal on silicon microdisplay driver for projection display has been designed and fabricated using AMI 0.5 µm double-poly, triple-level metal CMOS process. The driver includes frame buffering at the pixel level, which presents optimized optical characteristics for field sequential color operation, and a mixed mode gray scale method which implements distinct 256 gray levels per color with a simpler driver architecture.