James Donald Wagoner

A double precision floating point multiply

A 2.2GHz 53/spl times/54 bit pipelined multiplier is fabricated in 130nm CMOS technology with an area of 0.15mm/sup 2/. The circuit implementation results in a 50% size reduction over the previously reported values. The circuit operates at 2.2GHz and uses 522mW at 80% switching factor, 1.2V supply and 25/spl deg/C.

Design and implementation of the POWER5/spl trade/ microprocessor

POWER5/sup TM/ is the next generation of IBMs POWER microprocessors. This design, sets a new standard of server performance by incorporating simultaneous multithreading (SMT), an enhanced distributed switch and memory subsystem supporting 164w SMP, and extensive RAS support. First pass hardware using IBMs 130nm silicon-on-insulator technology operates above 1.5GHz at 1.3V. POWER5s dual-threaded SMT creates up to two virtual processors per core, improving execution unit utilization and masking memory latency. Although a simplistic SMT implementation promised /spl sim/20% performance improvement, resizing critical microarchitectural resources almost doubles in many cases the SMT performance benefit at a 24% area. Implementing these microarchitectural enhancements posed challenges in meeting the chips frequency, area, power, and thermal targets.