James J.-Q. Lu

First-order performance prediction of cache memory with wafer-level 3D integration

The advantages of 3D design can be exploited by reducing the memory access time. In this article, the authors use a simulator based on analytical models to build an optimal processor-memory configuration for two designs: a graphics processor and a microprocessor. One emerging alternative approach to relieving these interconnect constraints is the use of wafer-level 3D integration, which provides a high density of high-performance, low-parasitic vertical interconnects. A wafer-level 3D design is partitionable into multiple chips connected by short vertical vias. This arrangement reduces the length of many global interconnects without introducing any logic complexity. Wafer-level 3D integration also reduces the required number of repeaters, thereby improving the area efficiency and reducing the power consumed within the interconnect network. With micron-size interwafer vias, wafer-level 3D integration allows a large memory bandwidth with little wafer area consumption. We have developed a software program that allows a first-order comparison of cache designs in 2D and 3D IC technologies. We present a first-order estimate of the performance improvements achieved by 3D implementation of cache memory, with emphasis on large caches in deep-submicron technologies.

Wafer-to-Wafer Alignment for Three-Dimensional Integration: A Review

This paper presents a review of the wafer-to-wafer alignment used for 3-D integration. This technology is an important manufacturing technique for advanced microelectronics and microelectromechanical systems, including 3-D integrated circuits, advanced wafer-level packaging, and microfluidics. Commercially available alignment tools provide prebonding wafer-to-wafer misalignment tolerances on the order of 0.25 μm. However, better alignment accuracy is required for increasing demands for higher density of through-strata vias and bonded interstrata vias, whereas issues with wafer-level alignment uniformity and reliability still remain. Three-dimensional processes also affect the alignment accuracy, although the misalignment could be reduced to certain extent by process control. This paper provides a comprehensive review of current research activities over wafer-to-wafer alignment, including alignment methods, accuracy requirements, and possible misalignments and fundamental issues. Current misalignment concerns of the major bonding approaches are discussed with detailed alignment results. The fundamental issues associated with wafer alignment are addressed, such as alignment mechanisms, uniformity, reproducibility, thermal mismatch, and materials. Alternative alignment approaches are discussed, and perspectives for wafer-to-wafer alignment are given.

3-D Data Storage, Power Delivery, and RF/Optical Transceiver—Case Studies of 3-D Integration From System Design Perspectives

Three-dimensional (3-D) integration of systems by vertically stacking and interconnecting multiple materials, technologies, and functional components offers a wide range of benefits, including speed, bandwidth and density increase, power reduction, small form factor, packaging reduction, yield and reliability increase, flexible heterogeneous integration with multifunctionality, and overall cost reduction. A new spectrum of opportunities and challenges arises for integrated system designers, which warrants rethinking and innovations from system design perspectives. By selecting three representative cases, i.e., solid-state data storage, power delivery, and hybrid radio-frequency/optical transceiver for distributed sensor networks, this paper intends to exemplify the potentials of exploiting the benefits of 3-D integration technology from system perspectives.

Backside TSV protrusion induced by thermal shock and thermal cycling

This paper reports on thermal-mechanical failures of through-silicon-vias (TSVs), in particular, for the first time, the protrusions at the TSV backside, which is exposed after wafer bonding, thinning and TSV revealing. Temperature dependence of TSV protrusion is investigated based on wide-range thermal shock and thermal cycling tests. While TSV protrusion on the TSV frontside is not visible after any of the tests, protrusions on the backside are found after both thermal shock tests and thermal cycling tests at temperatures above 250°C. The average TSV protrusion height increases from ~0.1 μm at 250°C to ~0.5 μm at 400°C and can be fitted to an exponential function with an activation energy of ~0.6eV, suggesting a Cu grain boundary diffusion mechanism.

Design of 3D DRAM and Its Application in 3D Integrated Multi-Core Computing Systems

This paper concerns appropriate 3D DRAM architecture design and the potential of using 3D DRAM to implement both L2 cache and main memory in 3D multi-core processor-DRAM integrated computing systems. We first present a coarse-grained 3D partitioning strategy for 3D DRAM design that can well exploit the benefits provided by 3D integration without incurring stringent constraints on through-silicon via (TSV) fabrications. Targeting multi-core processors, we further present design techniques that can effectively reduce the access latency of 3D DRAM L2 cache, hence improve the overall 3D integrated computing system performance. The effectiveness of these developed design techniques have been successfully evaluated based on CACTI-based memory modeling and full system simulations over a wide spectrum of multi-programmed workloads. Simulation results show that the proposed heterogeneous 3D DRAM design can improve the harmonic mean IPC by 23.9% on average compared with a baseline scenario using 3D DRAM only as the main memory.

Boron filling of high aspect ratio holes by chemical vapor deposition for solid-state neutron detector applications

A multiple deposition and etching process has been developed to enable high fill factor boron deposition in high aspect ratio holes fabricated in a (100) silicon substrate. The boron deposition was carried out using low-pressure chemical vapor deposition and the etching was done by inductively coupled plasma reactive ion etching technique. The boron deposition processes were carried out under different conditions in order to find a baseline process condition. The boron etching processes done under different conditions with the photoresist as the mask are also discussed. Finally, the fabricated neutron detector with the highest fill factor was characterized for the thermal neutron detection efficiency.

Electromagnetic-Simulation Program With Integrated Circuit Emphasis Modeling, Analysis, and Design of 3-D Power Delivery

Accurate modeling and estimation of 3-D power network electrical performance are vitally important to aid 3-D integration and packaging design. This paper, for the first time, combines the electromagnetic (EM) simulation program with integrated circuit emphasis simulations to evaluate the electrical performance of a 3-D power network, which consists of Cu through-silicon-vias (TSVs), solders, micro-solders, and on-chip power grids. We intentionally partition a real stack-up structure of 3-D power network into separated components, electromagnetically extract all the passive elements resistance, inductance, conductance, and capacitance (RLGC) for each component at certain frequency points of interest. We then assemble all the components again into a corresponding equivalent circuit model and import EM-extracted RLGC values to analyze the overall 3-D system power performance. The number of stacked integrated circuits, floorplanning of TSVs/micro-solders, operating frequency of 3-D system, characteristics of decoupling capacitance, size of on-chip power grids, parasitics of power wires/vias/solders/TSVs/micro-solders, voltage supply, and waveform parameters of current loads are examined, unveiling several 3-D power delivery design implications.

High detection efficiency micro-structured solid-state neutron detector with extremely low leakage current fabricated with continuous p-n junction

We report the continuous p-n junction formation in honeycomb structured Si diode by in situ boron deposition and diffusion process using low pressure chemical vapor deposition for solid-state thermal neutron detection applications. Optimized diffusion temperature of 800 °C was obtained by current density-voltage characteristics for fabricated p+-n diodes. A very low leakage current density of ∼2 × 10−8 A/cm2 at −1 V was measured for enriched boron filled honeycomb structured neutron detector with a continuous p+-n junction. The neutron detection efficiency for a Maxwellian spectrum incident on the face of the detector was measured under zero bias voltage to be ∼26%. These results are very encouraging for fabrication of large area solid-state neutron detector that could be a viable alternative to 3He tube based technology.

Solid-state neutron detectors based on thickness scalable hexagonal boron nitride

This paper reports on the device processing and characterization of hexagonal boron nitride (hBN) based solid-state thermal neutron detectors, where hBN thickness varied from 2.5 to 15 μm. These natural hBN epilayers (with 19.9% 10B) were grown by a low pressure chemical vapor deposition process. Complete dry processing was adopted for the fabrication of these metal-semiconductor-metal (MSM) configuration detectors. These detectors showed intrinsic thermal neutron detection efficiency values of 0.86%, 2.4%, 3.15%, and 4.71% for natural hBN thickness values of 2.5, 7.5, 10, and 15 μm, respectively. Measured efficiencies are very close (≥92%) to the theoretical maximum efficiencies for corresponding hBN thickness values for these detectors. This clearly shows the hBN thickness scalability of these detectors. A 15 μm thick hBN based MSM detector is expected to yield an efficiency of 21.4% if enriched hBN (with ∼100% 10B) is used instead of natural hBN. These results demonstrate that the fabrication of hBN th...

Modeling and Analysis of PDN Impedance and Switching Noise in TSV-Based 3-D Integration

This paper reports on modeling and analysis of power delivery network (PDN) impedance and switching noise in through silicon via (TSV)-based 3-D integration. PDN is simulated in SPICE with the combination of lumped-element models and distributed-element models, where the elements are extracted from full-wave electromagnetic modeling. PDN impedance explicitly distinguishes the contributions from off-chip PDN and on-chip PDN, and reveals the TSV-induced resonant effect associated with the 3-D chip stack. The simultaneously switching noises in PDN are simulated and analyzed in different frequency regions, in which 3-D integration has distinct impacts on the PDN impedance.