Ronald J. Gutmann

Chemical Mechanical Planarization of Microelectronic Materials

Historical perspective CMP: variables and manipulations electrochemical and mechanical concepts for CMP processes copper CMP CMP of other materials post CMP cleaning.

Adhesive wafer bonding

Wafer bonding with intermediate polymer adhesives is an important fabrication technique for advanced microelectronic and microelectromechanical systems, such as three-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive bears the forces involved to hold the surfaces together. The main advantages of adhesive wafer bonding include the insensitivity to surface topography, the low bonding temperatures, the compatibility with standard integrated circuit wafer processing, and the ability to join different types of wafers. Compared to alternative wafer bonding techniques, adhesive wafer bonding is simple, robust, and low cost. This article reviews the state-of-the-art polymer adhesive wafer bonding technologies, materials, and applications.

Advanced multilayer metallization schemes with copper as interconnection metal

Abstract Advanced metallization schemes are needed to take advantage of the miniaturization of microelectronic devices which are performing at increasingly high speeds. The demands on metallization center around (a) the increased resistance with lower cross-sectional areas and longer interconnect lengths and (b) stability with the surroundings during processing and use under high current densities and thin film stresses. A threefold attack is being pursued to solve these problems, which also duplicate the issues in packaging of these fast chips with large numbers of inputs and outputs: first is to make use of copper as the interconnection metal; second is to use a multilevel metallization scheme; finally there is a need for a low dielectric constant dielectric. In this paper we present a review of progress made in addressing the first two schemes together with a brief discussion of the third. Copper, a heretofore undesired metal in silicon integrated circuits, seems to show promise, with appropriate processing constraints, of fulfilling the projected needs of ultra-large-scale and giga-scale integration and perhaps even of packaging.

Recombination processes in doubly capped antimonide-based quaternary thin films

Recombination processes in antimonide-based materials for thermophotovoltaic (TPV) devices have been investigated using a radio-frequency (rf) photoreflectance technique, in which a Nd–YAG pulsed laser is used to excite excess carriers, and the short-pulse response and photoconductivity decay are monitored with an inductively coupled noncontacting rf probe. Both lattice-matched AlGaAsSb and GaSb have been used to double cap InGaAsSb active layers to evaluate bulk lifetime and surface recombination velocity with different active layer thicknesses. With an active layer doping of 2×1017 cm−3, effective bulk lifetimes of 95 ns and surface recombination velocities of 1900 cm/s have been obtained. As the laser intensity is increased the lifetime decreases, which is attributed to radiative recombination under these high-level injection conditions. Similar measurements have been taken on both TPV device structures and starting substrate materials for comparison purposes.

Chemical processes in the chemical mechanical polishing of copper

The mechanisms by which removal and planarization occur during the chemical mechanical polishing (CMP) of copper, used for pattern delineation in a multilevel metallization scheme, are investigated in this paper. We propose that removal occurs as mechanical abrasion of the surface followed by chemical dissolution of the abraded species. Planarization is achieved by the use of a rigid polishing pad that provides mechanical abrasion only to the high areas on the copper surface and by the formation of a surface layer on the copper during polishing to prevent dissolution of copper in the low areas. Fundamentals of electrochemistry are used to explain and predict both the dissolution of copper and the formation of a surface layer in the CMP slurry. Examples of polishing slurries are presented to demonstrate our hypotheses, including a complexing agent (ammonia) plus oxidizer (ferricyanide ion or nitrate ion) slurry and an oxidizing acid (nitric acid) plus corrosion inhibitor (benzotriazole) slurry. Finally, the mechanisms used to explain the CMP of copper are used to explain anomalous behavior during the CMP of titanium, in which the presence of copper ions in the polish slurry accelerates the polish rate of titanium. Titanium is used as a diffusion barrier and adhesion promoter for copper.

Pattern Geometry Effects in the Chemical‐Mechanical Polishing of Inlaid Copper Structures

We describe an investigation into the pattern dependence of dishing and erosion during the chemical‐mechanical polishing of copper used for delineating inlaid metal patterns. Copper dishing is determined to be highly dependent on the width of the copper structure, but only minimally dependent on the density of copper structures. Erosion of the dielectric layer is strongly affected by the pattern density, but not affected by changes in the width of the copper lines. As a result, both line width and pattern density are important considerations in predicting the final thickness of the copper lines.

High-voltage normally off GaN MOSFETs on sapphire substrates

Gallium nitride self-aligned MOSFETs were fabricated using low-pressure chemical vapor-deposited silicon dioxide as the gate dielectric and polysilicon as the gate material. Silicon was implanted into an unintentionally doped GaN layer using the polysilicon gate to define the source and drain regions, with implant activation at 1100/spl deg/C for 5 min in nitrogen. The GaN MOSFETs have a low gate leakage current of less than 50 pA for circular devices with W/L=800/128 /spl mu/m. Devices are normally off with a threshold voltage of +2.7 V and a field-effect mobility of 45 cm/sup 2//Vs at room temperature. The minimum on-resistance measured is 1.9 m/spl Omega//spl middot/cm/sup 2/ with a gate voltage of 34 V (W/L=800/2 /spl mu/m). High-voltage lateral devices had a breakdown voltage of 700 V with gate-drain spacing of 9 /spl mu/m (80 V//spl mu/m), showing the feasibility of self-aligned GaN MOSFETs for high-voltage integrated circuits.

Application of RF Circuit Design Principles to Distributed Power Converters

The application of RF circuit design principles to high-frequency power converters is described. Compared to conventional converter design, emphasis is placed on obtaining sinusoidal-type waveforms (instead of rectangular-type waveforms) to minimize device switching time requirements and alleviate transforming requirements. A 25-W 48-V to 5-V dc-to-dc converter design using a 5-MHz switching frequency is presented illustrating these principles, using a Class E power amplifier, an L section impedance transformer, and a shunt-mounted harmonically tuned rectifier circuit. Computer simulation results are presented that indicate the feasibility of the proposed design approach, specify required circuit parameters and indicate that line and load regulation can be achieved with narrow-band frequency control. Experimental results on a low power 5-W, 25-V to 5-V dc-to-dc converter breadboard using a 10-MHz switching frequency with the described circuit topology are presented. An efficiency of 68 percent was obtained and load regulation by frequency control demonstrated. Inductor Q requirements limit the conversion efficiency of the proposed converter, and will probably be the limiting factor in obtaining high efficiency with similar design approaches.

Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics

The impact of interconnection parasitic inductance on MOSFET switching characteristics is modeled analytically and evaluated experimentally. Closed-form analytical equations are derived to evaluate switching characteristics due to common source inductance and switching loop inductance. Assuming an identical total parasitic inductance, a MOSFET with higher common source inductance has higher switching energy loss but lower overshoot voltage than a MOSFET with higher switching loop inductance. The tradeoffs between switching loss and signal overshoot and oscillation are included in design criteria for optimizing switching performance of packaged power electronics. The experimental results are in good agreement with the analytical modeling.

Electrical characteristics of GaAs MIS Schottky diodes

Abstract The current-voltage (I-V) and capacitance-voltage (C-V) characteristics of GaAs metal-insulator-semiconductor (MIS) Schottky barrier diodes are investigated over a wide temperature range and compared with MS diodes. The effects of the insulating layer on barrier height and carrier transport are delineated by an activation energy analysis. Excess currents observed at low forward and reverse bias have also been analyzed and their cause identified. A capacitance anomaly consistently noticed in MIS Schottky barriers is resolved by stipulating a non-uniform interfacial layer, and a self-consistent model of the GaAs MIS Schottky barrier is developed by analyzing I-V and C-V data of both MIS and MS diodes.