Dingyou Zhang

Successful void free gap fill of 3µm, high AR via middle, Through Silicon Vias at wafer level

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, Through Silicon Vias (TSV), of 3μm top entrant critical dimension (CD) and 50μm depth. Higher AR TSV integration is explored due to the lower stress influence of TSVs observed in adjacent CMOS devices.

TSV residual Cu step height analysis by white light interferometry for 3D integration

Cu pumping, or the extrusion of Cu out of a TSV after being subjected to high temperature conditions, is one of the highest risk failure modes to be overcome in the development of TSV-middle integration for 3D packaging technologies. Typical Cu pumping analyses focus on a low number of data points through brute force measurement using cross sectional analysis. The low number of data points gathered for each condition does not provide results with a high statistical confidence level. In addition, it is most likely that the cross section does not provide measurement along the plane that contains the highest amount of Cu pumping, resulting in inaccurate maximum pumping height measurements. In this study, a Cu pumping measurement technique was developed using a production capable scanning white light interferometry (SWLI) system, which enables the collection of hundreds or thousands of individual TSV Cu pumping data points. This enables an accurate statistical comparison between Cu pumping mitigation schemes. Using this technique, multiple TSV plating process and thermal annealing conditions were compared by varying temperature and time to determine the conditions that resulted in the lowest amount of Cu pumping. In addition, an alternate integration scheme was investigated that includes multiple anneal and CMP planarization steps. The experimental results demonstrate that Cu pumping can be kept to a manageable level for high reliability performance.

Process Development and Optimization for 3

This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 μm top entrant critical dimension and 50 μm depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 μm TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating.

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This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented along with their respective resistance, capacitance and leakage current data. The characterization and reliability results are presented through TSV daisy chain structures and MOL via chains.

High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level

High aspect ratio through silicon vias (TSV) present a challenge for measurement of bottom critical dimension (BCD) and depth. TSVs smaller than 5 micron diameter with greater than 12:1 depth to BCD aspect ratio have particularly poor signal to noise ratio in the measured signal. This paper proposes a method for improving the interferometric measurement of these very small and high-aspect ratio TSVs with data showing the feasibility of measuring both BCD and depth of 19:1 aspect ratio TSVs. This work demonstrates the capability to analyze the scanning white-light interferometry (SWLI) signal for such high aspect ratio TSV BCD and depth measurements with >0.95 R2 correlation to reference metrology obtained through cross section SEM. Precision of within 2.5% of nominal BCD and within 0.1% of nominal depth was demonstrated for 10x repeatability measurements.

Challenges to via middle TSV integration at sub-28nm nodes

Etch is one of the most critical processes for high-aspect ratio TSV as it defines the profile and wafer level depth uniformity of TSV, thus having a great impact on other downstream processes in TSV module and TSV backside reveal. This paper presents the challenges encountered in developing the 6μm × 55μm TSV (6μm diameter × 55μm depth) with a number of continuous process optimizations. These include improvements to the notch below the hard-mask, an increase in the post-etch resist retention, within wafer depth uniformity and higher silicon etch rate improving the throughput. TSV scaling to 3μm × 50μm with a higher aspect ratio is also demonstrated. This paper also describes details for setup of an Automatic Process Controller (APC) for TSV depth control in a manufacturing environment.

New interferometric measurement technique for small diameter TSV

To date, Plasma Enhanced Chemical Vapor Deposition (PECVD) O3/TEOS has been the prevalent dielectric liner for TSV applications. This process typically results in poor step coverage for high aspect ratio (HAR) TSV scenarios, and also requires a capping layer to provide acceptable reliability performance due to the high moisture content of the O3/TEOS material. This study reports on a high throughput room temperature Atomic Layer Deposition (ALD) batch process for use as a dielectric liner in TSV applications, which provides several advantages over existing processes. Process characterization was completed to achieve a 100nm thickness SiO2 liner for a 6×55μm TSV size with nearly 100% conformal sidewall coverage, demonstrating the usefulness of this process for scaling to 3×50μm TSV size and beyond. Characterization of the ALD SiO2 dielectric liner showed breakdown voltage, leakage, and parasitic capacitance values as good as, or better than, the PECVD O3/TEOS dielectric process of record. In addition, the batch ALD process allows for a significant cost reduction of the overall TSV module. The new ALD SiO2 dielectric liner material was also validated through the downstream TSV fabrication process with no adverse effects.

Process development and optimization for high-aspect ratio through-silicon via (TSV) etch

A novel “adaptive pattern registration” method is developed which gives a reliable estimate of various film thickness in a wafer level TSV. The film thickness are measured using picosecond ultrasonic metrology technique. The adaptive pattern registration method provides higher measurement accuracy at reduced cycle time in comparison to Scanning White-Light Interferometry based technique. It will be shown that TaN/Ta (barrier), Cu Seed and Cu plating film thickness measured at wafer level correlates well to the film thickness at the infield TSV level. The effect of these film thickness on electrical performance of the TSVs will also be discussed.

Room temperature ALD oxide liner for TSV applications

3D integration technology offers an alternative to traditional packaging designs. In traditional Moore’s law scaling, features are added to the die, with graphics, memory control and logic coprocessors all integrated onto the silicon chip. TSV (through silicon via) processing utilizes vertical electrical interconnects that provide the shortest possible path to establish an electrical connection from the device side to the backside of a die. This indirectly allows continues “Moore”- like scaling while only affecting the device packaging. White light interferometry (WLI) has been used for the measurement of topography, step height and via depth using its short coherence length. The nanometer level resolution of this technique is ideal for TSV measurements in the high aspect ratio vias. In this work, six white light interferometer measurements for TSV processing are discussed along with the importance of these measurements to TSV processing, namely: 1. Post-TSV etch: depth, top CD (TCD) and bottom CD (BCD) 2. Post-TSV liner BCD 3. Post-TSV barrier seed BCD 4. TSV electro-chemically plated (ECP) copper bump step height 5. Post-annealing bump step height 6. TSV CMP dishing These measurement steps have been implemented in-line for advanced technology node TSV process flows at GLOBALFOUNDRIES. The measurements demonstrate 90% correlation to reference metrology and <0.5% repeatability. Cross section SEM was used as a reference for TSV profile and Cu bump measurements while AFM was used as a reference for dishing measurements.