James M. Oberschmidt

Alternating phase-shifted mask for logic gate levels, design, and mask manufacturing

While the benefits of alternating phase shifted masks in improving lithographic process windows at increased resolution are well known throughout the lithography community, broad implementation of this potentially powerful technique has been slow due to the inherent complexity of the layout design and mask manufacturing process. This paper will review a project undertaken at IBMs Semiconductor Research and Development Center and Mask Manufacturing and Development facility to understand the technical and logistical issues associated with the application of alternating phase shifted mask technology to the gate level of a full microprocessor chip. The work presented here depicts an important milestone toward integration of alternating phase shifted masks into the manufacturing process by demonstrating an automated design solution and yielding a functional alternating phase shifted mask. The design conversion of the microprocessor gate level to a conjugate twin shifter alternating phase shift layout was accomplished with IBMs internal design system that automatically scaled the design, added required phase regions, and resolved phase conflicts. The subsequent fabrication of a nearly defect free phase shifted mask, as verified by SEM based die to die inspection, highlights the maturity of the alternating phase shifted mask manufacturing process in IBMs internal mask facility. Well defined and recognized challenges in mask inspection and repair remain and the layout of alternating phase shifted masks present a design and data preparation overhead, but the data presented here demonstrate the feasibility of designing and building manufacturing quality alternating phase shifted masks for the gate level of a microprocessor.

Improving yield through the application of process window OPC

As the industry progresses toward more challenging patterning nodes with tighter error budgets and weaker process windows, it is becoming clear that current single process condition Optical Proximity Corrections (OPC) as well as OPC verification methods such as Optical Rules Checking (ORC) performed at a single process point fail to provide robust solutions through process. Moreover, these techniques can potentially miss catastrophic failures that will negatively impact yield while surely failing to capitalize on every chance to enhance process window. Process-aware OPC and verification algorithms have been developed [1,2] that minimize process variability to enhance yield and assess process robustness, respectively. In this paper we demonstrate the importance of process aware OPC and ORC tools to enable first time right manufacturing solutions, even for technology nodes prior to 45nm such as a 65nm contact level, by identifying critical spots on the layout that became significant yield detractors on the chip but nominal ORC could not catch. Similarly, we will demonstrate the successful application of a process window OPC (PWOPC) algorithm capable of recognizing and correcting for process window systematic variations that threaten the overall RET performance, while maintaining printed contours within the minimum overlay tolerances. Direct comparison of wafer results are presented for two 65nm CA masks, one where conventional nominal OPC was applied and a second one processed with PWOPC. Thorough wafer results will show how our process aware OPC algorithm was able to address and successfully strengthen the lithography performance of those areas in the layout previously identified by PWORC as sensitive to process variations, as well as of isolated and semi-isolated features, for an overall significant yield enhancement.

New ESCAP-type resist with enhanced etch resistance and its application to future DRAM and logic devices

This new photoresist system extends the capability of the ESCAP platform previously discussed. (1) This resist material features a modified ESCAP type 4-hydroxystyrene-t-butyl acrylate polymer system which is capable of annealing due to the increased stability of the t-butyl ester blocking group. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus previous DUV resists, APEX and UV2HS. Improved stabilization of chemically amplified photoresist images can be achieved through reduction of film volume by film densification. When the host polymer provides good thermal stability the soft bake conditions can be above or near the Tg (glass transition) temperature of the polymer. The concept of annealing (film densification) can significantly improve the environmental stability of the photoresist system. Improvements in the photoacid generator, processing conditions and overall formulation coupled with high NA (numerical aperture) exposure systems, affords linear lithography down to 0.15 micrometer for isolated lines with excellent post exposure delay stability. In this paper, we discuss the UV4 and UV5 photoresist systems based on the ESCAP materials platform. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus APEX-E and UV2HS. Due to lower acrylate content, the Rmax for this system can be tuned for feature-type optimization. We demonstrate sub-0.25 micrometer process window for isolated lines using these resists on a conventional exposure tool with chrome on glass masks. We also discuss current use for various device levels including gate structures for advanced microprocessor designs. Additional data will be provided on advanced DRAM applications for 0.25 micrometer and sub-0.25 micrometer programs.

Automation of Sample Plan Creation for Process Model Calibration

The process of preparing a sample plan for optical and resist model calibration has always been tedious. Not only because it is required to accurately represent full chip designs with countless combinations of widths, spaces and environments, but also because of the constraints imposed by metrology which may result in limiting the number of structures to be measured. Also, there are other limits on the types of these structures, and this is mainly due to the accuracy variation across different types of geometries. For instance, pitch measurements are normally more accurate than corner rounding. Thus, only certain geometrical shapes are mostly considered to create a sample plan. In addition, the time factor is becoming very crucial as we migrate from a technology node to another due to the increase in the number of development and production nodes, and the process is getting more complicated if process window aware models are to be developed in a reasonable time frame, thus there is a need for reliable methods to choose sample plans which also help reduce cycle time. In this context, an automated flow is proposed for sample plan creation. Once the illumination and film stack are defined, all the errors in the input data are fixed and sites are centered. Then, bad sites are excluded. Afterwards, the clean data are reduced based on geometrical resemblance. Also, an editable database of measurement-reliable and critical structures are provided, and their percentage in the final sample plan as well as the total number of 1D/2D samples can be predefined. It has the advantage of eliminating manual selection or filtering techniques, and it provides powerful tools for customizing the final plan, and the time needed to generate these plans is greatly reduced.

Failure prediction across process window for robust OPC

In conventional Optical and Process Correction (OPC), models are calibrated with the CD measurement from the “good” printable patterns. Predictions of process window loss are based on extrapolation from the “good” region into the failure region. The extrapolation is always a less accurate process than interpolation. In this paper, we utilize the experimental pass/fail data to build models that accurately identify and predict printing failures. We developed a methodology and a formal apparatus for failure modeling. It is found that two or more aerial image shape parameters are required to describe all failure mechanisms for a sub-100nm process. This empirical failure model is currently applied to Optical Rule Checking (ORC) of the post-OPC layout. It also can be used to constrain layout corrections in the future.

The effect of OPC optical and resist model parameters on the model accuracy, run time, and stability

Performing model based optical proximity correction (MB-OPC) is an essential step in the production of advanced integrated circuits manufactured with optical lithography technology. The accuracy of these models highly depends on the experimental data used in the model development and on the appropriate selection of the model parameters. The optical and resist model parameters selected during model build have a significant impact on the OPC model accuracy, run time, and stability. In order to avoid excessively high run times as well as ensure acceptable results, a compromise must be made between OPC run time and model accuracy. The modeling engineer has to optimize the necessary model parameters in order to find a good trade-off that achieves acceptable accuracy with reasonable run time. In this paper, we investigate the effect of some selected optical and resist model parameters on the OPC model accuracy, run time, and stability.

Model-based calculation of weighting in OPC model calibration

Optimal Proximity Correction (OPC) models are calibrated with Scanning Electron Microscope (SEM) data where the measurement uncertainty vary among pattern types (i.e., line versus space, 1D versus 2D and small versus large). The quality of the SEM measurement uncertaintys impact on OPC model integrity is mitigated through a weighting scheme. Statistical methods such as relating the weight to the SEM measurements standard deviation require more measurements per calibration structure than economically feasible. Similarly, the use of experience and engineering judgment requires many iterations before some reasonable weighting scale is determined. In this paper we present the results of OPC model fitness statistics associated with metrology based weights (MtBW) versus model based weights (MBW). The motivation for the latter approach is the promise for an unbiased, consistent, and efficient estimate of the model parameters.

The effect of calibration feature weighting on OPC optical and resist models : investigating the influence on model coefficients and on the overall model fitting

Performing model based optical proximity correction (MB-OPC) is an essential step in the production of advanced integrated circuits that are manufactured with optical lithography technology. The accuracy of these models depends highly on the experimental data used in the model development (model calibration) process. The calibration features are weighted relative to each other depending on many aspects, this weighting plays an important role in the accuracy of the developed models. In this paper, the effect of the feature weighting on OPC models is studied. Different weighting schemes are introduced and the effect on both the optical and resist models (specifically the resist model coefficients) is presented and compared. The effect of the weighting on the overall model fitting was also investigated.

Challenges of implementing contour modeling in 32nm technology

Optical Proximity Correction (OPC) Model Calibration has required an increasing number of measurements as the critical dimension tolerances have gotten smaller. Measurement of two dimensional features have been increasing at a faster rate than features with one dimensional character as the technologies require better accuracy in the OPC models for line-end pull-back and corner rounding. New techniques are becoming available from metrology tool manufacturers to produce GDSII contours of shapes from wafers and modeling software has been improved to use these contours. The challenges of implementing contour generation from the SEM tools will be discussed including calibration methods, physical dimensions, algorithm derivations, and contour registration, resolution, scan direction, and parameter space coverage.

Overlay measurement and analysis of x-ray/optical lithography for mix-and-match device applications

A joint Motorola/IBM experiment was performed in mix-and-match lithography across widely separated locations. A simple pattern placement metrology data set was created, and x-ray masks were manufactured according to this data. The same data was converted into a 5x reticle and optically stepped on wafers. The x-ray mask was designed to print upon two optical fields with one x-ray exposure. The x-ray mask was aligned to the wafers to produce box-in- box images for overlay metrology. The main overlay problems encountered were systematic offsets between x-ray and optical images, and average magnification error of approximately 8 ppm. The magnification error is substantial because of the 3 degree(s)C temperature difference between the optical stepper stage and the x-ray mask-writer. In an actual device run, the magnification differences will be removed by compensation in the e-beam writing of the x-ray mask. Offsets will be removed by use of a send-ahead wafer to determine the correct offset alignment in the x-ray stepper.