Liam Madden

A 200-MHz 64-b dual-issue CMOS microprocessor

A RISC (reduced-instruction-set computer)-style microprocessor operating up to 200 MHz, implements a 64-b architecture that provides huge linear address space without bottlenecks that would impede highly concurrent implementations. Fully pipelined and capable of issuing two instructions per clock cycle, this implementation can execute up to 400 M operations per second. The chip includes an 8-kB I-cache, an 8-kB D-cache, and two associated translation buffers, a four-entry 32-B/entry write buffer, a pipelined 64-b integer execution unit with 32-entry register file, and a pipelined floating-point unit with an additional 32 registers. The pin interface includes integral support for an external secondary cache. The package is a 431-pin PGA with 140 pins dedicated to VDD/VSS. The chip is fabricated in 0.75- mu m n-well CMOS with three layers of metallization. The die measures 16.8*13.9 mm/sup 2/ and contains 1.68 M transistors. Power dissipation is 30 W from a 3.3-V supply at 200 MHz. >

6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters

A reconfigurable heterogeneous 3D-IC is assembled from two 28 nm FPGA die with 580 k logic cells and two 65 nm mixed signal die on a 65 nm interposer in a 35 mm 2 CS-BGA package. One mixed signal die consists of sixteen 16 bit current steering DACs, the other die consists of sixteen 13 bit pipelined ADCs. The interposer provides optimal system partitioning; noise isolation and high density interconnect between subsystems. Receive SNDR > 61.6 dBFS to Nyquist at 500 MS/s and transmit SFDR > 63.8 dBc to 400 MHz at 1.6 GS/s is measured. Ultralow FPGA to converter die interface power of 0.3 mW/Gb/s is achieved and measured digital to analog isolation > 92dB. The solution can be dynamically optimized for channel count, power and speed.

Reliability evaluation of a CoWoS-enabled 3D IC package

TSV (Through Silicon Via)-based interposer has been proposed as a multi-die package solution to meet the rapidly increasing demand in inter-component (e.g. CPU, GPU and DRAM) communication bandwidth in an electronic system. The stacked-silicon die package configuration may give rise to package reliability concerns not observed in conventional monolithic flip-chip packages. 3D finite element method (FEM) was used to study the thermo-mechanical response of the interposer-based package during thermal cycle reliability stressing. Fatigue failures of the C4 and BGA joints are the two primary reliability focuses in the present study. Experimental data collected on the CoWoS™-enabled test vehicles were used to validate the FEM models. Parametric study of key package material and geometric parameters was performed to analyze their effects on C4 bump thermal cycle reliability. Package materials of interest include UF (underfill), lid and substrate, and the geometric parameters include lid thickness and C4 bump scheme. The results showed that the CoWoS package using AlSiC lid has better C4 bump life than the CoWoS package using Cu lid, and when the Tg of the underfill of C4 bump is higher, the C4 bump has better reliability. Furthermore, 3D thermo-mechanical and reliability study of BGA balls is presented for organic and ceramic substrates. Several DOEs have been constructed for ceramic substrate to increase BGA reliability by optimizing C4 underfill material and package design. The effect of board layer count and design is detailed. Finally reliability of BGA balls, C4 and micro-bumps are compared for a part that is mounted on a PCB board.

Advancing high performance heterogeneous integration through die stacking

This paper describes the industrys first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). Each device is housed in a low-temperature co-fired ceramic (LTCC) package for optimal signal integrity. Inside the package, a heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic solution. Mounted on a passive silicon interposer with through-silicon vias (TSVs), the heterogeneous IC stack comprises FPGA ICs with 13.1-Gb/s transceivers and dedicated analog ICs with 28-Gb/s transceivers. Optimization took place concurrently on multiple facets of the design which were necessary to successfully implement the 3-D integration. In particular, this paper outlines the choices that were made in terms of package substrate material and interposer resistivity in order to optimize 28Gb/s system channel characteristics. These choices were validated through extensive electrical simulation and test chip correlation. In addition, this paper describes the design and timing verification of inter-die interconnects, an area that the electronic design automation industry had not yet fully addressed. This paper further describes 3D thermal-mechanical modeling and analysis for package reliability. The modeling was performed to address package coplanarity issues and stresses imposed by the interposer on the active dice, the low-k dielectric material, the micro-bumps and the C4 attach. The results indicate heterogeneous stacked-silicon (3D) integration is a reliable method to build very high-bandwidth multi-chip devices that exceed current monolithic capabilities.

Heterogeneous 3-d stacking, can we have the best of both (technology) worlds?

Since the advent of integrated circuit technology in 1958, the industry has focused primarily on monolithic integration. Unfortunately, due to physical and economic issues, the vast majority of high performance analog chips, high density memory chips, and high performance digital chips are each built on separate technologies. Therefore, in order to deliver optimum system performance, power and cost, it is desirable to integrate multiple different die, each using its own optimized technology, in a single package. This paper describes the industrys first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration). The heterogeneous IC stack delivers up to 2.78Tb/s transceiver bandwidth. The resulting bandwidth is approximately three times that achievable in a monolithic solution. Mounted on a passive silicon interposer with through-silicon vias (TSVs), the heterogeneous IC stack comprises FPGA ICs with 13.1-Gb/s transceivers and dedicated analog ICs with 28-Gb/s transceivers.