James O. Hamblen

Computer algorithms for plagiarism detection

A survey of computer algorithms used for the detection of student plagiarism is presented. A summary of several algorithms is provided. Common features of the different plagiarism detection algorithms are described. Ethical and administrative issues involving detected plagiarism are discussed. >

Rapid prototyping using field-programmable logic devices

Traditionally, undergraduates in electrical and computer engineering study the design and implementation of a simple computer and then develop their own designs. In recent years, computer design courses have for the most part taken a simulation-only approach. Rapid prototyping techniques and a new generation of large field-programmable logic devices (FPLDs) enabled an educational approach that combines modeling with hardware description languages (HDLs), extensive simulation, synthesis, and final verification on a hardware prototype. The author describes an undergraduate computer engineering curriculum using a rapid prototyping approach to simulate, synthesize, and implement digital system and computer architectures.

An introductory digital design course using a low-cost autonomous robot

This paper describes a new digital design laboratory developed for undergraduate students in this electrical and computer engineering curriculum. A top-down rapid prototyping approach with commercial computer-aided design tools and field-programmable logic devices (FPLDs) is used for laboratory projects. Students begin with traditional transistor-transistor logic-based projects containing a few gates and progress to designing a simple 16-bit computer, using very high-speed integrated circuits hardware description language (VHDL) synthesis tools and an FPLD. To help motivate students, the simple computer design is programmed to control a small autonomous robot with two servo drive motors and several sensors. The laboratory concludes with a team-based design project using the robot.

An undergraduate computer engineering rapid systems prototyping design laboratory

This paper describes a new two-quarter undergraduate capstone design class in our computer engineering curriculum. Design groups comprised of students from several different areas of specialization (e.g., software systems, very large scale integration (VLSI) devices and circuits, and computer architecture) design, simulate, implement, and evaluate a complete computing system. Typical examples of projects in the current sequence include a pipelined 32-bit RISC processor, a four-cell systolic array processor, and a video game. The goal is to produce simulation and hardware/software codesign as early as possible in the design process. Students execute software on simulation models prior to any hardware implementation. An assembler and a compiler are developed for the new design. Throughout the sequence, students participate in design reviews and must provide documentation of their designs. The final designs are implemented using an array of field programmable gate arrays (FPGAs) contained in a device called a hardware emulator. This allows for ease of design modifications while still having actual hardware for experimentation.

An Embedded Systems Laboratory to Support Rapid Prototyping of Robotics and the Internet of Things

This paper describes a new approach for a course and laboratory designed to allow students to develop low-cost prototypes of robotic and other embedded devices that feature Internet connectivity, I/O, networking, a real-time operating system (RTOS), and object-oriented C/C++. The application programming interface (API) libraries provided permit students to work at a higher level of abstraction. A low-cost 32-bit SOC RISC microcontroller module with flash memory, numerous I/O interfaces, and on-chip networking hardware is used to build prototypes. A cloud-based C/C++ compiler is used for software development. All student files are stored on a server, and any Web browser can be used for software development. Breadboards are used in laboratory projects to rapidly build prototypes of robots and embedded devices using the microcontroller, networking, and other I/O subsystems on small breakout boards. The commercial breakout boards used provide a large assortment of modern sensors, drivers, display ICs, and external I/O connectors. Resources provided include eBooks, laboratory assignments, and extensive Wiki pages with schematics and sample microcontroller application code for each breakout board.

Using a Low-Cost SoC Computer and a Commercial RTOS in an Embedded Systems Design Course

This paper describes our experiences using a low-cost SoC embedded computer system and a commercial RTOS for a senior level embedded system design class. The eBox 2300 is a small low-cost X86 SoC computer system. It has all of the I/O features typically found in a standard PC. Windows Embedded CE 6.0 is a widely used hard real-time operating system (RTOS). This course covers both hardware and software topics in embedded systems. The course culminates in a final team-based design project. A full set of course materials including a textbook with laboratory tutorials was developed and is available at the course web site.

Using an FPGA Processor Core and Embedded Linux for Senior Design Projects

This paper describes our experiences using a low-cost SoPC FPGA board and an open source RTOS for senior design projects. The Altera DE2 is a small low- cost FPGA-based SoPC system designed for educational use. It has many of the VO features typically found in a standard PC and can support a Nios soft processor core. Students developed a custom Nios processor design for the board and customized a muClinux OS to support their senior design projects.

The design of a neural network with a biologically motivated architecture

An associative neural network whose architecture is greatly influenced by biological data is described. The proposed neural network is significantly different in architecture and connectivity from previous models. Its emphasis is on high parallelism and modularity. The network connectivity is enriched by recurrent connections within the modules. Each module is, effectively, a Hopfield net. Connections within a module are plastic and are modified by associative learning. Connections between modules are fixed and thus not subject to learning. Although the network is tested with character recognition, it cannot be directly used as such for real-world applications. It must be incorporated as a module in a more complex structure. The architectural principles of the proposed network model can be used in the design of other modules of a whole system. Its architecture is such that it constitutes a good mathematical prototype to analyze the properties of modularity, recurrent connections, and feedback. The model does not make any contribution to the subject of learning in neural networks.

On the behavior of some associative neural networks

Since Hopfield published his work on an associative memory model, a large number of works have studied the model from several angles and showed in particular its weaknesses, and presented ways to overcome them. Most of the proposed solutions seem to us however not biologically plausible. In this paper we present a simple statistical analysis of two networks similar to the Hopfield net, and show that the usage of positive feedback enhances the net recognizing capability without jeopardizing the stability. We also describe a layered parallel network composed of modules, each module being a modified Hopfield net. We finally present computer simulation results to support our analytical findings. The most important principles of this network are supported by data from the world of neurobiology.

Parallel continuous system simulation using the Transputer

Parallel processing methods can be used to decrease the solu tion time of simulation models. Techniques are shown for the parallel solution of a continuous system simulation using digital hardware. Using a new VLSI single chip computer, the TRANS puter, a simple parallel digital computer system is constructed and its performance is evaluated on two example problems.