James P. Rice

Embedded DRAM: technology platform for the Blue Gene/L chip

The Blue Gene®/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is the simultaneous instantiation of multiple PowerPC® cores, high-performance static random access memory (SRAM), DRAM, and several other logic design blocks on a single-platform technology. The IBM embedded DRAM platform allows this seamless integration without compromising performance, reliability, or yield. We discuss the process architecture, the key parameters of the logic components used in the processor cores and other logic design blocks, the SRAM features used in the L2 cache, and the embedded DRAM that forms the L3 cache. We also discuss the evolution of embedded DRAM technology into a higher-performance space in the 90-nm and 65-nm nodes and the potential for dynamic memory to improve overall memory subsystem performance.

Yield Learning Methodology in Early Technology Development

Yield learning during early technology development is critical to ensuring successful integration of new process technologies, meeting development schedules, and transitioning smoothly into manufacturing. However, yield learning in early technology development is very different from yield learning in manufacturing. This paper will discuss the unique challenges of yield learning in early technology development. To meet these challenges, innovative systematic and parametric yield models were developed to address many new issues that arose in early 45 nm development at IBM. Furthermore, to understand and characterize new yield loss mechanisms, innovative characterization methods were developed. This paper will illustrate the unified yield learning methodology in early technology development which combines these various yield models and methods to establish a grand pareto and a yield step-up plan to prioritize the whole technology development efforts.