Xu Ouyang

Yield Learning Methodology in Early Technology Development

Yield learning during early technology development is critical to ensuring successful integration of new process technologies, meeting development schedules, and transitioning smoothly into manufacturing. However, yield learning in early technology development is very different from yield learning in manufacturing. This paper will discuss the unique challenges of yield learning in early technology development. To meet these challenges, innovative systematic and parametric yield models were developed to address many new issues that arose in early 45 nm development at IBM. Furthermore, to understand and characterize new yield loss mechanisms, innovative characterization methods were developed. This paper will illustrate the unified yield learning methodology in early technology development which combines these various yield models and methods to establish a grand pareto and a yield step-up plan to prioritize the whole technology development efforts.

Yield monitor for embedded-sige process optimization

If not yield optimized, embedded SiGe (eSiGe) processes with aggressive transistor performance enhancements could induce high SRAM standby current and single cell failures in SRAM. In order to optimize the yield of eSiGe process, a SRAM-layout-based test structure was identified. It has the advantage of being able to be tested after silicidation or first metal level, therefore can be used as an early monitor of yield degradation due to eSiGe and therefore an effective vehicle for optimization between yield and performance. Using this monitoring structure, an eSiGe process optimized for yield was developed which does not show additional yield loss due to eSiGe while retaining comparable performance enhancements.