James S. Golab

DFT advances in the Motorola's MPC7400, a PowerPC/sup TM/ G4 microprocessor

Several advances have been made in the design for testability of the MPC7400, the first fourth generation PowerPC microprocessor. The memory array built-in self-test algorithms now support detecting write-recovery defects and more comprehensive diagnostics. Delay defects can be tested with scan patterns with the phased locked loop providing the at-speed launch-capture events. Several methodology and modeling improvements increased LSSD stuck-at fault test coverage. Design for manufacturability enhancements provide better tracking of initial silicon and fuse-based memory repair capabilities for improved yield and time-to-market.

Next generation PowerPC/sup TM/ microprocessor test strategy improvements

The first PowerPC microprocessor in the new G3 generation of designs, the MPC750, incorporates new test strategy approaches to improve the product test quality, reliability, and debug, and to reduce the total time to market.

Test strategy for the PowerPC 750 microprocessor

Time-to-market goals are intricately entwined with the product testing strategy for a high-performance microprocessor. The result is an on-time product introduction coupled with improved, more effective and thorough testing.