Rajesh Raina

Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC/spl trade/ instruction set architecture

Scan based at-speed transition fault testing of Motorolas microprocessors based on the PowerPC/spl trade/ instruction set architecture requires broad-side transition fault test patterns that have a specific launch and capture clocking sequence. We describe the concepts we developed and incorporated in the ATPG tool to support efficient generation of such test patterns to achieve high transition fault test coverage and for analysis of undetected transition faults. Using the enhanced ATPG tool, we generated 15,000 transition fault test patterns and achieved 76% test coverage for the MPC7400 microprocessor based on the PowerPC/spl trade/ instruction set architecture that has 10.5 million transistors and runs at 540 MHz.

Use of DFT techniques in speed grading a 1 GHz+ microprocessor

This paper presents a practical case-study of using DFT techniques for speed-grading the Motorola MPC7455, a 1 GHz+ microprocessor. The effectiveness of transition fault detection, path-delay AC-scan patterns and array BIST is compared with that of functional patterns for speed-grading the parts. We discuss the capabilities and challenges of using the DFT methods based on production data.

Functional verification methodology for the PowerPC 604 microprocessor

Functional (i.e., logic) verification of the current generation of complex, super-scalar microprocessors such as the PowerPC 604 microprocessor presents significant challenges to a projects verification participants. Simple architectural level tests are insufficient to gain confidence in the quality of the design. Detailed planning must be combined with a broad collection of methods and tools to ensure that design defects are detected as early as possible in a projects life-cycle. This paper discusses the methodology applied to the functional verification of the PowerPC 604 microprocessor.

At-speed testing of delay faults for Motorola's MPC7400, a PowerPC/sup TM/ microprocessor

In this paper we present the novel built-in delay fault test concepts incorporated into Motorolas MPC7400 PowerPC microprocessor that allow us to use a slow speed tester to do at-speed, scan based, delay fault testing. A novel feature of the design is the programmable clock control circuit for issuing a given number of at-speed clocks for the delay test, once the test is initiated. Using transition and path delay fault test patterns, we have tested several MPC7400 chips at speed exceeding 540 MHz using tester speed of 63 MHz or lower.

DFT advances in the Motorola's MPC7400, a PowerPC/sup TM/ G4 microprocessor

Several advances have been made in the design for testability of the MPC7400, the first fourth generation PowerPC microprocessor. The memory array built-in self-test algorithms now support detecting write-recovery defects and more comprehensive diagnostics. Delay defects can be tested with scan patterns with the phased locked loop providing the at-speed launch-capture events. Several methodology and modeling improvements increased LSSD stuck-at fault test coverage. Design for manufacturability enhancements provide better tracking of initial silicon and fuse-based memory repair capabilities for improved yield and time-to-market.

DFT advances in Motorola's Next-Generation 74xx PowerPC/sup TM/ microprocessor

This paper shares techniques used to overcome DFT challenges on Motorolas Next-Generation 74xx PowerPC/sup TM/ microprocessor-a 700+ MHz microprocessor with an on-chip, 256 K byte second-level cache.

Testing clock distribution circuits using an analytic signal method

This paper presents an application of a new analytic signal method for measuring clock skews in the clock distribution network of microprocessors. The method can measure skews between the master system clock and distributed clocks, between two distributed clocks, or between clocks whose frequencies are related by frequency division. Experimental data using a PowerPC/sup TM/ microprocessor is presented for validation.

Design-for-test methodology for Motorola PowerPC/sup TM/ microprocessors

Testing of modern microprocessor designs remains a challenging problem. At Motorolas Somerset Design Center, we rely heavily on Design-For-Test (DFT) to address these challenges. To date our efforts have been very successful. This paper reviews our DFT methodology and how the DFT group is dealing with the new challenges that are facing PowerPC/sup TM/ microprocessor designs.

Random self-test method applications on PowerPC/sup TM/ microprocessor caches

This paper describes a novel method for generating test stimuli for digital systems. By taking advantage of certain properties of the Design Under Validation, the method can be used to generate test stimuli that are random as well as self-testing. We discuss the requirements and limitations of this method on practical designs. The use of this method for High-Level Design Validation of caches in PowerPC/sup TM/ microprocessors is also described. The paper concludes by identifying areas where further work is needed.

Skew measurements in clock distribution circuits using an analytic signal method

This paper presents the application of a new analytic signal method for measuring several different kinds of clock skew in the clock distribution network of microprocessors. First, key terms are defined, and other existing skew measurement methods are reviewed. Then, detailed steps are given for applying the new method for measuring skew between a master and distributed clocks, between two distributed clocks, and between different frequency clocks that are related by frequency division. An indirect procedure for measuring deterministic clock skew is also proposed. Next, the new method is validated with experimental data from a prototype microprocessor test. Performance comparison is performed between the analytic signal method and the two-probe method. Finally, the measurement requirements of the proposed analytic signal method are compared with those of conventional methods.