James T. Cargo

Backside failure analysis and case studies for Cu/low k technology

In this work, failure analysis (FA) challenges and new failure modes for devices of copper technology, especially for circuit-under-pad (CUP) devices are presented. Backside FA techniques including backside sample preparation, backside defect localization, backside physical analysis with both deprocessing and cross section analysis have been developed and applied to Cu/low k technology. For backside FA deprocessing, we present wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and combination of these techniques. For the backside FA cross-section analysis of copper/low k samples, focused ion beam (FIB) techniques that have been developed and studied are addressed. In addition, detailed characterization of backside silicon thinning using TMAH wet chemicals is presented.

Physical failure analysis deprocessing and cross-section techniques for Cu/low-k technology

In this paper, physical failure analysis (FA) techniques including interconnect level and gate level deprocessing techniques and cross section analysis that have been developed will be discussed. Deprocessing techniques discussed include: wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP), and combinations of these techniques. Moreover, the detailed characterization of CMP process and gate level deprocessing will be presented. For the cross-section analysis of copper/low-k samples, focused ion beam (FIB) and mechanical polishing techniques will be discussed. FA challenges and new failure modes and reliability issues will also be addressed.

Characterization of reactive ion etching of polysilicon over gate oxide for failure mode analysis deprocessing

There is not much work reported for RIE of polysilicon for FMA and moreover, there are still many challenging issues for RIE of poly silicon including etch selectivity, surface roughness, poly residues and the optimization of the process parameters. In this work, we have studied the poly silicon etching characteristics for chlorine and fluorine based RIE systems. We investigated the dependence of poly etch rate and etch selectivity on the process parameters including O/sub 2/ flow, chamber pressure, ICP power and RIE power. The goal of this work was to characterize the effects of process parameters on etch rate, etch selectivity and surface roughness for the etching of poly silicon over gate oxide in FMA de-processing.

Overview of Cu/low K technology failure analysis and reliability issues

Failure Analysis (FA) challenges and issues in several areas, such as physical FA, site identification, and backside FA will be addressed. New failure modes, reliability issues for advanced technology, especially for Cu/Low-k technology, and advanced FA techniques will also be discussed. For physical FA, we will discuss wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and combinations of these techniques. For site identification techniques, we will address photon based techniques, laser/electron beam based scanning systems, and electrical testing techniques. Backside FA techniques have become increasingly important for advanced technology. In this work, several backside sample preparation techniques and backside site identification techniques will also be discussed.

Characterization of various etching techniques for gate level failure analysis and substrate decoration for advanced Cu/low k technologies

In this paper, VLSI technology scaling trends and challenges will be addressed. Failure analysis (FA) challenges, and failure modes for advanced technologies will also be presented. Both Cu/low k integration and gate dielectric integration issues will be discussed, followed by characterization of various poly-silicon etches used for gate oxide decoration. Finally, several different silicon substrate decoration techniques will be presented.

Physical Failure Analysis techniques for Cu/low k technology

In this work, physical FA techniques including deprocessing and cross section analysis have been developed and applied to Cu/low k technology. Deprocessing techniques discussed include: wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and combination of these techniques. For the cross-section analysis of copper/low k samples, focused ion beam and mechanical polishing techniques have been developed and studied. Failure Analysis (FA) challenges and new failure modes, reliability issues will also be addressed.