James Victory

Accuracy of approximations in MOSFET charge models

This paper analyzes the results of common approximations made in MOSFET charge modeling. The basis for the comparison is a charge-sheet model that is valid in all regions of operation. We show that proper modeling of surface potential as a function of position along the channel is more important for capacitance coefficient modeling accuracy than partitioning of inversion charge between source and drain. In addition, we show that there is a numerical error in previous charge-sheet formulations, and provide a solution for this problem.

A physically based, scalable MOS varactor model and extraction methodology for RF applications

A physically based scalable model for MOS varactors, including analytical surface potential based charge modeling and physical geometry and process parameter based parasitic modeling, is proposed. Key device performances of capacitance and quality factor Q are validated over a wide voltage, frequency, and geometrical space. The model, implemented in Verilog-A for simulator portability, provides for robust and accurate RF simulation of MOS varactors.

Benchmark Tests for MOSFET Compact Models With Application to the PSP Model

This paper presents the results of several qualitative ldquobenchmarkrdquo tests that were used to verify the physical behavior of the PSP model and its usefulness for future generations of CMOS IC design. These include newly developed tests and new experimental data stemming from low-power, RF, mixed-signal, and analog applications of MOSFETs.

Statistical Modeling With the PSP MOSFET Model

PSP and the backward propagation of variance (BPV) method are used to characterize the statistical variations of metal-oxide-semiconductor field effect transistors (MOSFETs). BPV statistical modeling of NMOS and PMOS devices is, for the first time, coupled by including self-consistent modeling of ring oscillator gate delays. Parasitic capacitances are included in the analysis. The proposed technique is validated using Monte-Carlo simulations and by comparison to experimental data from two technologies.

PSP-Based Scalable MOS Varactor Model

A physically based scalable model for MOS Varactors is presented. The model includes a PSP-based analytical surface potential charge formulation, MOS varactor specific gate current models, and physical geometry and process parameter based parasitic modeling. Key device performances of capacitance and quality factor Q are validated over voltage, frequency, and geometry, for several technologies. The model, implemented in Verilog-A, provides robust and accurate RF simulation of MOS varactors. A VCO design application is detailed.

On the Performance of Multiobjective Evolutionary Algorithms in Automatic Parameter Extraction of Power Diodes

In this paper, a general, robust, and automatic parameter extraction of nonlinear compact models is presented. The parameter extraction is based on multiobjective optimization using evolutionary algorithms, which allow fitting of several highly nonlinear and highly conflicting characteristics simultaneously. Two multiobjective evolutionary algorithms which have been proved to be robust for a wide range of multiobjective problems [1]-[3], the nondominated sorting genetic algorithm II and the multiobjective covariance matrix adaptation evolution strategy, are used in the parameter extraction of a novel power diode compact model based on the lumped charge technique. The performance of the algorithms is assessed using a systematic statistical approach. Good agreement between the simulated and measured characteristics of the power diode shows the accuracy of the used compact model and the efficiency and effectiveness of the proposed multiobjective optimization scheme.

Improved Parameter Extraction Procedure for PSP-Based MOS Varactor Model

We present an improved procedure for extracting parasitic capacitance parameters and gate current parameters for MOSVAR, the industry standard MOS varactormodel. Our technique is verified against measured data from three technology nodes (180 nm, 130 nm and 65 nm), and is also used to validate the MOSVAR P-gate/P-well tunneling current sub-model.

A physically based scalable SPICE model for Shielded-Gate Trench Power MOSFETs

This paper proposes a novel physical scalable SPICE model for Shielded-Gate Trench Power MOSFETs. The model is based on process and layout parameters, enabling design optimization through a direct link between SPICE and process technology. The model has been validated with Fairchilds state of the art technology. The model is SPICE agnostic, working seamlessly across multiple industry standard simulation platforms.

Advances in LDMOS Compact Modeling for IC Design: The SP-HV Model and Its Capabilities

Lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors are key interfaces between digital CMOS circuits and the real analog world; they are widely used in high-voltage and high-current applications, but they can be exceedingly difficult to model accurately. This article reviews recent advances in the compact modeling of LDMOS transistors, with an emphasis on the surface-potential-based high-voltage MOS (SP-HV) model and its capabilities. Detailed physical analysis of experimentally observed complexities in LDMOS behavior are reviewed and the relevance to IC design of the advanced modeling capabilities of SP-HV are detailed.

Turn-off instabilities in large area IGBTs

Abstract In this paper, an experimental study is proposed to investigate the failure effects in IGBT large-area devices due to hard gate driving strategies. Thanks to quasi-3D simulations, a large overcurrent is predicted in few cells and corresponds to a large spike in the gate voltage during collector voltage transient, which is able to trigger the device instability. An interpretation of the phenomenon is given that attributes such spike to a strong current imbalance on the large area device, so that a latch-up failure mechanism is proposed.