Kenneth A. Townsend

Recent advances and future trends in low power wireless systems for medical applications

This paper describes current state-of-the-art research on low power wireless systems for medical applications. Distinct design criteria and challenges in this area are addressed. A study of existing wireless technologies and their key applications are presented. A brief assessment of future trends for wireless medicine with a focus on emerging technologies is provided. Finally, a number of different energy-scavenging techniques for the future development of autonomous wireless nodes are reviewed.

A Wideband Power Detection System Optimized for the UWB Spectrum

A wideband radio-frequency (RF) power detection system is presented. The detection technique uses NMOS devices operating in the triode regime to generate an average current proportional to RF input power; this current is converted to voltage and amplified using a piecewise linear logarithmic approximation. Optimization of the NMOS devices is discussed, and a method of gain control is proposed for compensation of temperature and process variation. The power detector occupies an active area of 0.36 mm2 in a 0.18 mum CMOS process and consumes 10.8 mW from the power supply. Error between the output and a linear-in-dB best-fit curve is plusmn2.4 dB for a 20 dB input range, when measured at discrete frequencies. The output response is frequency independent, varying by less than 1.8 dB for a fixed input power as frequency is swept across the UWB spectrum.

A fine-resolution Time-to-Digital Converter for a 5GS/S ADC

This paper presents the architecture of a high-speed time-based Analog-to-Digital Converter (ADC) based on voltage-to-time and time-to-digital conversion. A tunable Time-to-Digital Converter (TDC) that is robust against process variation and suitable for embedding within a 3-bit ADC is discussed and its performance evaluated. Simulation shows that when the TDC is designed in a 90nm CMOS process it is capable of a DNL and INL less than ±0.040L5B and ±0.015LSB, respectively, for 9mW of power consumption at 5GS/s with a 6.25ps resolution.

Ultra-Wideband Front-End With Tunable Notch Filter

This paper presents the design of an LNA with integrated tunable notch filter targeted for UWB receivers. Impulse-based UWB systems suffer from an increased BER in the presence of strong interferers due to reduced SNR. The first stage of the LNA achieves a wideband input match while the second stage employs an integrated bridged-T filter for interferer cancellation. The LNA has been implemented in a standard 0.18mum CMOS process. Simulated results show the notch filter is tunable from 3.5GHz to 7.0GHz with greater than 40dB of rejection. For a notch frequency of 5.3GHz, the noise figure and gain at 3.5GHz are 4.1dB and 12.1dB respectively

A CMOS Integrated Power Detector for UWB

An integrated CMOS RF power detector for wideband systems that does not require additional processing steps is presented. The received signal modulates the resistance of a MOSFET biased in triode to produce a DC current at the input of a transimpedance amplifier proportional to the received power. The resulting voltage is applied to an auto-zeroed logarithmic amplifier that provides offset cancellation without lowpass filtering. Simulation shows that the detector is capable of resolving a 40dB input dynamic range across the 3-10GHz UWB spectrum while dissipating less than 8mW.

Design and optimization of low-voltage low-power quasi-floating gate digital circuits

This paper explores the design and optimization of quasi-floating gate MOS techniques to low-voltage/low-power digital circuitry. The simulated power consumption of standard CMOS gates is compared to that of QFGMOS implementations in a 0.18/spl mu/m process for different supply voltages and device sizes. A 0.4V V/sub DD/ full-adder biased for propagation delay similar to that of 0.8V CMOS is simulated and shown to consume 1.2/spl mu/W for a 50MHz input, representing more than a 50% power reduction over the CMOS equivalent. A divide-by-16 circuit designed for operation at a maximum frequency of 400MHz uses 25/spl mu/W, 45/spl mu/W, and 75/spl mu/W for supplies of 0.4V, 0.6V and 0.8V.

RF CMOS circuits for ad-hoc networks and wearable computing

Wireless ad-hoc networks are gaining interest for medical, sensing, wearable computing and other applications. The industry is at a critical juncture now where the maturity of RF CMOS can enable these networks. All of these applications, if deployed successfully, results in the proliferation of wireless devices like we have never seen before. The end result is that these devices need to be very low cost, which fits in well with the CMOS paradigm. The challenge going forward is how to make CMOS RF circuits that consume ultra-low power in a compact form factor.

A 2.5GS/s 3-bit time-based ADC in 90nm CMOS

This paper describes the first gigasample rate time-based Nyquist analog-to-digital converter (ADC), consisting of a voltage-to-time-converter (VTC) followed by a time-to-digital- converter (TDC). After tuning, the 3-bit 2.5GS/s ADC designed in 90nm CMOS is measured to have an effective number of bits (ENOB) greater than 2.1 up to the Nyquist frequency. The power consumption, not including the TDC output drivers, is 12.1 mW.

An Image-Reject Low-Noise Amplifier with Passive Q-Enhanced Notch Filters

An image-reject low-noise amplifier with passive Q-enhanced notch filters in 0.18 mum CMOS is presented. Available IR-LNA designs employ a single notch filter to reject the precise image frequency and therefore require an additional automatic tuning circuit. This design achieves image-rejection over a bandwidth by using two series-connected passive notch filters, thereby relaxing the requirement of any additional tuning circuit. The proposed image-reject low noise amplifier has 16 dB gain at the signal frequency of 2.4 GHz and 58 dB rejection over a bandwidth of 100 MHz centered at the image frequency of 1.6 GHz. Noise Figure of 2.25 dB and P1dB of -13 dBm are obtained with bias current of 3.9 mA drawn from a 1.5 V power supply.

Low-power Q-enhancement for parallel LC tanks

A Q-enhancement technique based on active compensation of monolithic inductors for parallel resonant LC tanks is presented. Narrowband Q-enhancement is achieved using a gyrator to produce a negative inductance and negative resistance. The circuit is optimized for low-power operation and allows DC voltage control of Q-enhancement. A simulated two-stage capacitively-coupled Butterworth filter in 0.18mum CMOS consumes 1.9mW for a center frequency of 2.45GHz and a 100MHz bandwidth. The filter figure-of-merit is 135dBHz/mW