Jan C. van der Veen

An Exact Algorithm for Higher-Dimensional Orthogonal Packing

Higher-dimensional orthogonal packing problems have a wide range of practical applications, including packing, cutting, and scheduling. Combining the use of our data structure for characterizing feasible packings with our new classes of lower bounds, and other heuristics, we develop a two-level tree search algorithm for solving higher-dimensional packing problems to optimality. Computational results are reported, including optimal solutions for all two-dimensional test problems from recent literature. This is the third in a series of articles describing new approaches to higher-dimensional packing.

Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices

We describe algorithmic results for two crucial aspects of allocating resources on computational hardware devices with partial reconfigurability. By using methods from the field of computational geometry, we derive a method that allows correct maintainance of free and occupied space of a set of n rectangular modules in optimal time Θ(n log n); previous approaches needed a time of O(n 2 ) for correct results and O(n) for heuristic results. We also show that finding an optimal feasible communication-conscious placement (which minimizes the total weighted Manhattan distance between the new module and existing demand points) can be computed in Θ(n log n). Both resulting algorithms are practically easy to implement and show convincing experimental behavior.

PackLib2: An integrated library of multi-dimensional packing problems

Abstract We present PackLib2, the first fully integrated benchmark library for multi-dimensional packing instances. PackLib2 combines a systematic collection of all benchmark instances from previous literature with a well-organized set of new and challenging large instances. The XML format allows linking basic benchmark data with other important properties, like bibliographic information, origin, best known solutions, runtimes, etc. Transforming instances into a variety of existing input formats is also quite easy, as the XML format lends itself to easy conversion; for this purpose, a number of parsers are provided. Thus, PackLib2 aims at becoming a one-stop location for the packing and cutting community: in addition to fair and easy comparison of algorithmic work and ongoing measurement of scientific progress, it poses numerous challenges for future research.

Dynamic Defragmentation of Reconfigurable Devices

We propose a new method for defragmenting the module layout of a reconfigurable device, enabled by a novel approach for dealing with communication needs between relocated modules and with inhomogeneities found in commonly used FPGAs. Our method is based on dynamic relocation of module positions during runtime, with only very little reconfiguration overhead; the objective is to maximize the length of contiguous free space that is available for new modules. We describe a number of algorithmic aspects of good defragmentation, and present an optimization method based on tabu search. Experimental results indicate that we can improve the quality of module layout by roughly 50% over the static layout. Among other benefits, this improvement avoids unnecessary rejections of modules.

Minimizing Communication Cost for Reconfigurable Slot Modules

We discuss the problem of communication-aware module placement in array-like reconfigurable environments, such as the Erlangen Slot Machine (ESM). Bad placement of modules may degrade performance due to increased signal delays and wastes chip space for the reconfigurable multiple bus. We present integer linear programming (ILP) formulations that address both of these problems; both ILPs can be used stand-alone or as building blocks for more involved mathematical models. We validate our models by demonstrating their usefulness for a set of realistic benchmarks.

The Erlangen Slot Machine – A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens)

We introduce a hardware platform called Erlangen Slot Machine (ESM) that has been built in Erlangen within the project ReCoNodes for enabling interdisciplinary research on reconfigurable computing. For this dynamically reconfigurable computer, the cooperation partner in Braunschweig provides algorithmic solutions, in particular for the optimization of module placements and inter-module communication. Eine Hardware-Plattform mit Namen Erlangen Slot Machine (ESM) wird beschrieben, die im Projekt ReCoNodes in Erlangen entstanden ist. Sie soll dazu dienen, methodische Ansätze und Anwendungen anderer Projekte zu testen und interdisziplinär zugänglich zu machen. Der Kooperationspartner in Braunschweig liefert algorithmische Lösungen für diesen dynamisch rekonfigurierbaren Rechner, insbesondere zur Optimierung der Modulplatzierung und der Kommunikation zwischen Modulen.

ReCoNodes—Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices

Placement and scheduling are recognized as the most important problems when exploiting the benefit of partially reconfigurable devices such as FPGAs. For example, dynamically loading and unloading modules onto an FPGA causes fragmentation, and—in turn—may decrease performance. To counteract this effect, we use methods from algorithmics and mathematical optimization to increase the performance and present algorithms for placing, scheduling, and defragmenting modules on FPGAs. Taking communication between modules into account, we further present strategies to minimize communication overhead. Finally, we consider scheduling module requests with time-varying resource demands.

A minimization version of a directed subgraph homeomorphism problem

We consider a special case of the directed subgraph homeomorphism or topological minor problem, where the host graph has a specific regular structure. Given an acyclic directed pattern graph, we are looking for a host graph of minimal height which still allows for an embedding. This problem has applications in compiler design for certain coarse-grain reconfigurable architectures. In this application domain, the task is to simultaneously schedule, bind and route a so-called data-flow graph, where vertices represent operations and arcs stand for data dependencies between the operations, given an orthogonal grid structure of reconfigurable processing elements (PEs) that have restricted communication abilities. We show that the problem of simultaneously scheduling, binding and routing is NP-complete by describing a logic engine reduction from NAE-3-SAT. This result holds even when the input graph is a directed tree with maximum indegree two. We also give a |V|3/2-approximation algorithm.

Simultaneous Scheduling, Binding and Routing for Coarse-Grain Reconfigurable Architectures

A filter structure uses multiple discrete filter circuits which are cascaded to provide a multiple tap filter of programmable tap length. In one form, an FIR filter may be implemented wherein each circuit generates partial sum operands which must be added to provide a filter output. The cascaded circuits perform partial addition operations near simultaneously by using a serial addition which is synchronized with a start bit. The number of taps in the filter structure implemented by the cascaded discrete filter circuits is variable and may be programmed with a programmable storage register in each discrete circuit which stores operand data fixing the tap length of each discrete circuit. The multiple filter circuits provide a single filter structure with a large tap length and high sampling rate.