Mateusz Majer

DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices

A new paradigm to support the communication among modules dynamically placed on a reconfigurable device at run-time is presented. Based on the network on chip (NoC) infrastructure, we developed a dynamic communication infrastructure as well as routing methodologies capable to handle routing in a NoC with obstacles created by dynamically placed components. We prove the unrestricted reachability of components and pins, the deadlock-freeness and we finally show the feasibility of our approach by means on real life example applications.

The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-based Computer

Computer architects have been studying the dynamically reconfigurable computer (Schaumont, Verbauwhede, Keutzer, and Sarrafzadeh, “A Quick Safari through the Reconfiguration Jungle,” in Proc. of the 38th Design Automation Conference, Las Vegas, pp. 127–177, 2001) for a number of years. New capabilities such as on-demand computing power, self-adaptiveness and self-optimization capabilities by restructuring the hardware on the fly at run-time is seen as a driving technology factor for current research initiatives such as autonomic (Kephart and Chess, Computer, 36:41–52, 2003; IBM Autonomic Computing Initiative, (http://www.research.ibm.com/autonomic/)) and organic computing (Müller-Schloer, von der Malsburg, and Würtz, Inform.-Spektrum, 27:332–336, 2004; The Organic Computing Page, (http://www.organic-computing.org)). Much research work is currently devoted to models for partial hardware module relocation (SPP1148 Reconfigurable Computing Priority Program, (http://www12.informatik.uni-erlangen.de/spprr/)) and dynamically reconfigurable hardware reconfiguration on e.g., FPGA-based platforms. However, there are many physical restrictions and technical problems limiting the scope or applicability of these approaches. This led us to the development of a new FPGA-based reconfigurable computer called the Erlangen Slot Machine. The architecture overcomes many architectural constraints of existing platforms and allows a user to partially reconfigure hardware modules arranged in so-called slots. The uniqueness of this computer stems from (a) a new slot-oriented hardware architecture, (b) a set of novel inter-module communication paradigms, and (c) concepts for dynamic and partial reconfiguration management.

Packet routing in dynamically changing networks on chip

On-line routing strategies for communication in a dynamic network on chip (DyNoC) environment are presented. The DyNoC has been presented as a medium supporting communication among modules which are dynamically placed on a reconfigurable device at run-time. Using simulation, we compare the performance of an adaptive Q-routing algorithm to the well known XY-routing strategy. Both algorithms are adapted to support communication on the DyNoC which is equivalent to routing on meshes with obstacles. In our experiments, Q-routing proves its performance under varying network load while using only local information for its routing decisions.

A practical approach for circuit routing on dynamic reconfigurable devices

Management of communication by on-line routing in new FPGAs with a large amount of logic resources and partial re configurability is a new challenging problem. A network-on-chip (NoC) typically uses packet routing mechanism, which has often unsafe data transfers, and network interface overhead. In this paper, circuit routing for such dynamic NoCs is investigated, and a practical 1-dimensional network with an efficient routing algorithm is proposed and implemented. Also, this concept has been extended to the 2-dimensional case. The implementation results show the low area overhead and high performance of this network.

The Erlangen Slot Machine: a highly flexible FPGA-based reconfigurable platform

We present a new concept as well as the implementation of an FPGA-based reconfigurable platform, the Erlangen Slot Machine (ESM). The main advantages of this platform are: first, the possibility for each module to access its peripheries independent from its location through a programmable crossbar, and distributed SRAMs among slices. This allows an unrestricted relocation of modules on the device. Second, the intermodule structure allows an unlimited communication among running modules.

Task scheduling for heterogeneous reconfigurable computers

We consider the problem of executing a dynamically changing set of tasks on a reconfigurable system, made upon a processor and a reconfigurable device. Task execution on such a platform is managed by a scheduler that can allocate tasks either to the processor or to the reconfigurable device. The scheduler can be seen as part of an operating system running on the software or as core in the reconfigurable device. For each tasks to be executed on reconfigurable device, an equivalent implementation exists as rectangular block in a database. This block has to be placed on the device at run-time. A placer is responsible for the placement of tasks received from the scheduler on the reconfigurable device. However, the placement of tasks on the reconfigurable device cannot be successful if enough space is not available on the device to hold the task. In this case, the scheduler receive an acknowledgment from the placer and decide either to preempt a running task or to run the task on software. We present in this work an implementation of a placer module as well as investigations on task preemption. The two modules are part of an operating system for reconfigurable system currently under development.

Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device

Modern generations of field-programmable gate arrays (FPGAs) allow for partial reconfiguration. In an online context, where the sequence of modules to be loaded on the FPGA is unknown beforehand, repeated insertion and deletion of modules leads to progressive fragmentation of the available space, making defragmentation an important issue. We address this problem by proposing an online and an offline component for the defragmentation of the available space. We consider defragmenting the module layout on a reconfigurable device. This corresponds to solving a 2D strip packing problem. Problems of this type are NP-hard in the strong sense, and previous algorithmic results are rather limited. Based on a graph-theoretic characterization of feasible packings, we develop a method that can solve 2D defragmentation instances of practical size to optimality. Our approach is validated for a set of benchmark instances. We also discuss a simple strategy for dealing with online scenarios, called ldquoleast-interference fitrdquo (LIF); we give a number of analytic results that allow a comparison of LIF with the best offline solution, and demonstrate that it works well on benchmark instances of moderate size.

Minimizing Communication Cost for Reconfigurable Slot Modules

We discuss the problem of communication-aware module placement in array-like reconfigurable environments, such as the Erlangen Slot Machine (ESM). Bad placement of modules may degrade performance due to increased signal delays and wastes chip space for the reconfigurable multiple bus. We present integer linear programming (ILP) formulations that address both of these problems; both ILPs can be used stand-alone or as building blocks for more involved mathematical models. We validate our models by demonstrating their usefulness for a set of realistic benchmarks.

The Erlangen Slot Machine – A Platform for Interdisciplinary Research in Dynamically Reconfigurable Computing (ESM - Eine Hardware-Plattform für interdisziplinäre Forschung im Bereich des dynamischen rekonfigurierbaren Rechnens)

We introduce a hardware platform called Erlangen Slot Machine (ESM) that has been built in Erlangen within the project ReCoNodes for enabling interdisciplinary research on reconfigurable computing. For this dynamically reconfigurable computer, the cooperation partner in Braunschweig provides algorithmic solutions, in particular for the optimization of module placements and inter-module communication. Eine Hardware-Plattform mit Namen Erlangen Slot Machine (ESM) wird beschrieben, die im Projekt ReCoNodes in Erlangen entstanden ist. Sie soll dazu dienen, methodische Ansätze und Anwendungen anderer Projekte zu testen und interdisziplinär zugänglich zu machen. Der Kooperationspartner in Braunschweig liefert algorithmische Lösungen für diesen dynamisch rekonfigurierbaren Rechner, insbesondere zur Optimierung der Modulplatzierung und der Kommunikation zwischen Modulen.

ReCoNodes—Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices

Placement and scheduling are recognized as the most important problems when exploiting the benefit of partially reconfigurable devices such as FPGAs. For example, dynamically loading and unloading modules onto an FPGA causes fragmentation, and—in turn—may decrease performance. To counteract this effect, we use methods from algorithmics and mathematical optimization to increase the performance and present algorithms for placing, scheduling, and defragmenting modules on FPGAs. Taking communication between modules into account, we further present strategies to minimize communication overhead. Finally, we consider scheduling module requests with time-varying resource demands.