Jan Lohstroh

Static-noise margin analysis of MOS SRAM cells

The stability of both resistor-load (R-load) and full-CMOS SRAM cells is investigated analytically as well as by simulation. Explicit analytic expressions for the static-noise margin (SNM) as a function of device parameters and supply voltage are derived. The expressions are useful in predicting the effect of parameter changes on the stability as well as in optimizing the design of SRAM cells. An easy-to-use SNM simulation method is presented, the results of which are in good agreement with the results predicted by the analytic SNM expressions. It is further concluded that full-CMOS cells are much more stable than R-local cells at a low supply voltage.

ISL, a fast and dense low-power logic, made in a standard Schottky process

ISL is a new 200 mV voltage swing LSI-logic, made in a standard Schottky process, with a better speed, a 10 times lower power dissipation, and a 6 times better packing density than low power Schottky TTL.

Punch-through currents in P+NP+ and N+PN+ sandwich structures—I: Introduction and basic calculations

Abstract A qualitative description and a quantitative approximation of the current/voltage characteristic of the punch-through effect, based on drift- and diffusion-theory, is presented. An exact definition of the punch-through voltage is given. For small currents the current/voltage characteristic of the punch-through effect is an exponential curve i = I 0 exp [ q ( V − V PT )/ m ( i ) kT ] where m ( i ) is a non-ideality factor which is equal or larger than 2 and which increases with increasing current. At larger currents a deviation of the exponential curve is found due to space-charge limiting effects. A more general theory for small currents and some experimental verifications are described in Part II[48].

Punch-through currents in P+NP+ and N+PN+ sandwich structures—II: General low-injection theory and measurements

Abstract Analytical one-dimensional exponential expressions are derived for the current/voltage characteristics of the punch-through effect in devices where a certain bias voltage is needed to bring the device into punch-through ( V PT > 0) and where punch-through is already present in the non-biased condition ( V PT = 0). Measurements show that the theory can describe the current/voltage relations adequately at low current levels.

Performance, temperature behavior, and first-order modeling of ISL

The minimum propagation delay time of integrated Schottky logic (ISL) made in a standard LS process is determined by saturation of the vertical p-n-p clamp transistor. A performance improvement is obtained by increasing the dope of the substrate to prevent this saturation effect. When using 5 /spl mu/m minimum dimensions the minimum propagation delay is then well below 3 ns over the full temperature range from -55 up to 150/spl deg/C chip temperature. It is shown that a vertical p-n-p clamp transistor is essential to obtain a high speed when relaxed design rules are used. Furthermore, it is shown that ISL can be modeled in a relatively simple manner with one n-p-n transistor and one or two p-n-p transistors, depending on the resistivity of the substrate.

Dynamic behavior of active charge in I/sup 2/L transistors calculated with lumped transistor models

In this paper, a base for further detailed I/SUP 2/L lumped modeling work is given. The lumped model is used because of its close contact with internal physical processes. Transmission line effects can be included, using multilump models. Excess minority carrier plots, which can be derived from internal node voltages, visualize very clearly the behavior of the active charge. As an example, a transient calculation is presented in which the minimum delay time is calculated. It appears that the relatively thick n-epi emitter of the inverse operated n-p-n transistor determines the switching behavior. Some measurements done with ring oscillators indicate that short ring oscillators give too optimistic delay times.