Jan Schier

Scheduling of Iterative Algorithms with Matrix Operations for Efficient FPGA Design--Implementation of Finite Interval Constant Modulus Algorithm

This paper deals with the optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in Field Programmable Gate Arrays (FPGA), using Integer Linear Programming (ILP). The method is demonstrated on an implementation of the Finite Interval Constant Modulus Algorithm. It is an equalization algorithm, suitable for modern communication systems (4G and behind). For the floating-point calculations required in the algorithm, two arithmetic libraries were used in the FPGA implementation: one based on the logarithmic number system, the other using floating-point number system in the standard IEEE format. Both libraries use pipelined modules. Traditional approaches to the scheduling of nested loops lead to a relatively large code, which is unsuitable for FPGA implementation. This paper presents a new high-level synthesis methodology, which models both, iterative loops and imperfectly nested loops, by means of the system of linear inequalities. Moreover, memory access is considered as an additional resource constraint. Since the solutions of ILP formulated problems are known to be computationally intensive, an important part of the article is devoted to the reduction of the problem size.

Efficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm

This paper deals with the optimization of iterative algorithms with matrix operations or nested loops for hardware implementation in Field Programmable Gate Arrays (FPGA), using Integer Linear Programming (ILP). The method is demonstrated on an implementation of the Finite Interval Constant Modulus Algorithm, proposed for 4G communication systems. We used two pipelined arithmetic ibraries based on the logarithmic number system or the floating-point number system, using the widely known IEEE format for the floating-point calculations required in the algorithm. Traditional approaches to the scheduling of nested loops lead to a relatively large code, which is unsuitable for FPGA implementation. This paper presents a new high-level synthesis methodology, which models both, iterative loops and imperfectly nested loops, by means of the system of linear inequalities. Moreover, memory access is considered as an additional resource constraint. Since the solutionns of ILP formulated problems are known to be computationally intensive, important part of the article is devoted to the reduction of the problem size.

Optimization of finite interval CMA implementation for FPGA

The paper deals with optimization of an FPGA implementation of iterative algorithms with nested loops, using integer linear programming. The scheduling is demonstrated on an example of the FI-CMA blind equalization algorithm, with implementation using limited (and small) number of arithmetic units with non-zero latency. The optimization is based on cyclic scheduling with precedence delays for distinct dedicated processors. The approach is based on construction of an optimally scheduled abstract model, modeling imperfectly nested loops.

Logarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping

The paper is focused on the rapid prototyping for FPGA using the high-level environment of MATLAB/Simulink. An approach using the Xilinx system generator (XSG) is reviewed on an example of the high-speed logarithmic arithmetic (HSLA) unit. An alternative approach using the combination of the real time workshop (RTW) with the Handle-C compiler for automatized generation of the HDL code is presented. Finally, the possibilities to extend this solution in order to support the run-time reconfigurations are outlined.

Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA

In this paper, we outline an FPGA implementation of the QR update algorithm with Givens rotations using the High Speed Logarithmic Arithmetic (HSLA) library. An advantage of this approach is low latency and accurate computation (comparable with single-precision floating point) of the operations.

Estimation of transport delay using parallel recursive modified Gram–Schmidt algorithm

The paper describes a recursive algorithm for the estimation of transport delay. Based on the assumption that the delay is a discrete quantity with a finite number of values, the algorithm uses Bayesian probabilistic apparatus to test the probability of each possible value. The computation of probabilities uses the output of the recursive modified Gram–Schmidt (RMGS) algorithm. The result is a highly modular algorithm which may be implemented on parallel (VLSI) hardware and is hence suitable for applications requiring fast data processing.

FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic

Adaptive filters are used in many applications of digital signal processing. Digital communications and digital video broadcasting are just two examples. The GSFAP algorithm, discussed in the paper, is characterized by convergence superior to the popular NLMS, with only slightly higher complexity. The paper deals with floating-point-like implementation of algorithm using FPGA hardware. We present an optimized core for the GSFAP, built using logarithmic arithmetic which provides very low cost multiplication and division. The design is crafted to make efficient use of the pipelined logarithmic addition units. The resulting GSFAP core can be clocked at more than 80 MHz on the one million gate Xilinx XC2VI000-4 device. It can be used to implement filters of orders 20 to 1000 with a sampling rate exceeding 50 kHz. For comparison, we implemented a similar NLMS core and found that although it is slightly smaller than the GSFAP core and it allows a higher signal sampling rate (around 70 kHz) for the corresponding filter orders, GSFAP has adaptation properties that are much superior to NLMS, and that our core can provide very sophisticated adaptive filtering capabilities for resource-constrained embedded systems

Robust Adaptive Controller with Fine Grain Parallelism

Abstract Two issues associated with an adaptive linear quadratic controller are addressed in the paper: numerical robustness of the adaptive estimator with respect to low excitation in the closed control loop and rather high computational complexity of the controller. The algorithm presented in the paper uses The estimator used in the paper is based on the inverse-updated square-root recursive least squares (SR-RLS) identification algorithm (Moonen and McWhirter 1993). To increase numerical robustness of the algorithm for weak excitation, the regularized exponential forgetting is used. The multi-step control design uses an autoregression system model with exogenous input (ARX model). Computational complexity of the resulting algorithm is reduced by using the systolic paradigm for its implementation.