Jang-Sik Lee

Flexible organic transistor memory devices.

The flexible nonvolatile organic memory devices were developed on the plastic substrates based on the organic thin-film transistors embedding self-assembled gold nanoparticles (Au(NP)). The organic memory devices exhibited good programmable memory characteristics with respect to the program/erase operations, resulting in controllable and reliable threshold voltage shifts. Additionally, the endurance, data retention, and bending cyclic measurements confirmed that the flexible memory devices exhibited good electrical reliability as well as mechanical stability. The memory devices were composed of the solution-processed organic dielectric layers/metallic nanoparticles and the low-temperature processed organic transistors. Therefore, this approach could potentially be applied to advanced flexible/plastic electronic devices as well as integrated organic device circuits.

Plasma-Assisted Atomic Layer Growth of High-Quality Aluminum Oxide Thin Films

Thin aluminum oxide (Al2O3) films were grown by the plasma-assisted atomic layer controlled deposition (PAALD) method using Dimethylethylamine alane [(CH3)2(C2H5)N:AlH3] (DMEAA). Al was deposited by the PAALD method, then the Al films were oxidized into Al2O3 by plasma oxidation in the same chamber without breaking the vacuum. Al2O3 thin films of 15 nm thickness were prepared by repetition of this process. Thus prepared Al2O3 thin films exhibited a refractive index of 1.68. The thickness and the refractive index fluctuation of the film over a 4 inch wafer were ±2.3% and ±1.9%, respectively, for the deposited films. The leakage current density and breakdown field were measured to be about 10-8 A/cm2 at 1 MV/cm and 7 MV/cm, respectively. Considerable improvement of the electrical properties was realized by the post oxygen-plasma annealing at 200°C.

Highly Stable Transparent Amorphous Oxide Semiconductor Thin‐Film Transistors Having Double‐Stacked Active Layers

Recently, amorphous oxide semiconductors (AOSs) have extensively been studied for applications as display devices because AOSs have many advantages over conventional amorphous and polycrystalline silicon that are used for the channel layers of thin-fi lm transistors (TFTs). [ 1 ] As a representative AOS material, amorphous gallium-indium-zinc-oxide (a-GIZO) has intensively been studied as an active layer of TFTs for switching/driving devices in active-matrix liquid crystal display (AMLCD) and active-matrix organic light-emitting diode display (AMOLED) backplanes [ 2–5 ] because of its advantages, such as a good short-range uniformity, a high fi eld-effect mobility ( μ FE ), a large area uniform integration, a low cost and low temperature fabrication process, transparency, etc. Therefore, AOSs can be used in novel application areas, including transparent and/ or fl exible electronic devices. Up until now, many prototype active-matrix displays have been demonstrated, including 12.1 inch wide extended graphics array (WXGA) OLED displays, [ 2 ]

Flexible Hybrid Organic–Inorganic Perovskite Memory

Active research has been done on hybrid organic-inorganic perovskite materials for application to solar cells with high power conversion efficiency. However, this material often shows hysteresis, which is undesirable, shift in the current-voltage curve. The hysteresis may come from formation of defects and their movement in perovskite materials. Here, we utilize the defects in perovskite materials to be used in memory operations. We demonstrate flexible nonvolatile memory devices based on hybrid organic-inorganic perovskite as the resistive switching layer on a plastic substrate. A uniform perovskite layer is formed on a transparent electrode-coated plastic substrate by solvent engineering. Flexible nonvolatile memory based on the perovskite layer shows reproducible and reliable memory characteristics in terms of program/erase operations, data retention, and endurance properties. The memory devices also show good mechanical flexibility. It is suggested that resistive switching is done by migration of vacancy defects and formation of conducting filaments under the electric field in the perovskite layer. It is believed that organic-inorganic perovskite materials have great potential to be used in high-performance, flexible memory devices.

Reproducible resistance switching characteristics of hafnium oxide-based nonvolatile memory devices

The resistance switching characteristics of HfO2 thin films deposited by reactive sputtering were examined as a function of the annealing temperature. The results showed that the Pt/HfO2/Pt devices exhibited reversible and steady bistable resistance states [high-resistance state (HRS) and low-resistance state (LRS)]. Reproducible resistance switching from one state to another state or vice versa could be achieved by applying the appropriate voltage bias. The memory performances were related to the crystal structures of the HfO2 films, as confirmed by x-ray diffraction. From current-applied voltage analysis of the devices, LRS in the low electric field regime exhibited Ohmic conduction behavior, while HRS in the high electric field was followed by Poole–Frenkel conduction behavior. The resistance ratios of the two states were maintained in the range of around two orders of magnitude during the endurance test. In addition, it was confirmed that the resistance of the on and off states can be well maintained ...

Nonvolatile nano-floating gate memory devices based on pentacene semiconductors and organic tunneling insulator layers

Controlled gold nanoparticle (AuNP)-based nonvolatile memory devices were developed based on pentacene organic transistors and polymethylmethacrylate (PMMA) insulator layers. The memory device had the following configuration: n+Si gate/SiO2 blocking oxide/polyelectrolytes/AuNP/PMMA tunneling dielectric layer/Au source-drain. According to the programming/erasing operations, the memory device showed good programmable memory characteristics with a large memory window. In addition, good reliability was confirmed by the data retention characteristics. The fabrication procedures for the charge trapping and tunneling layers were based on simple solution processes (by dipping and spin-coating) and the maximum processing temperature was <100 °C, so this method has potential applications in plastic/flexible electronics.

Progress in non-volatile memory devices based on nanostructured materials and nanofabrication

Semiconductor device technology has continuously advanced through active research and the development of innovative technologies during the past decades. Semiconductor devices are expected to descend below the 10 nm scale within the next 10 years. Meanwhile, nanofabrication technology and the synthesis of nanostructured materials for novel device applications have made considerable progress too. This review will discuss new technologies that make this continuous device scaling possible. Then, recent efforts and research activities will be discussed regarding the fabrication and characterization of non-volatile memory devices made of nanostructured materials and by nanofabrication. This review concludes with an analysis of device fabrication strategies and device architectures beyond the device scaling limit with an emphasis on some promising technologies from bottom-up approaches.

Recent progress in gold nanoparticle-based non-volatile memory devices

Recently, much progress has been made toward the fabrication of non-volatile memory devices based on metallic nanoparticles. Among the many kinds of nanoparticles, gold nanoparticles are some of the most widely used materials for charge trapping elements in non-volatile memory devices because they are chemically stable, easily synthesized, and have a high work function. Various synthesis methods have been applied to fabricate gold nanoparticle-based nonvolatile memory devices and recent progress indicates that gold is a very promising material for non-volatile memory applications. In this article, the recent advances in fabrication and characterization of gold nanoparticle-based nonvolatile memory devices, with an emphasis on flash memory-type memory devices, are reviewed. Detailed device fabrication, characterization, and future directions are reported based on the recent research activities and literature.

A novel NAND-type MONOS memory using 63nm process technology for multi-gigabit flash EEPROMs

A NAND-type MONOS device has been successfully developed by breakthrough technologies including optimized cell structures and integration schemes providing favorable memory cell structures and peripheral circuits. In this study, optimized TANOS (TaN-Al2O 3-nitride-oxide- silicon) cells integrated using 63nm NAND flash technology showed high performance compatible to floating-gate (FG) cell. The newly-developed TANOS-NAND flash technology proved to be a promising candidate to replace FG memory beyond 50nm technology

Multilevel Data Storage Memory Devices Based on the Controlled Capacitive Coupling of Trapped Electrons

Since the fi rst conceptualization of non-volatile memory devices using a fl oating gate in 1967, [ 1 ] tremendous efforts have been made to develop high-density, low-cost, and non-volatile solidstate memory devices for portable electronics. [ 2–17 ] Among the many kinds of non-volatile memory devices, fl ash memories which use an array of fl oating gate transistors to store information are the most widely used. [ 12–20 ] One of the main limitations of conventional fl ash memory devices is the easy discharge of the stored information from the fl oating gate to the silicon substrates through the thin tunneling oxide. [ 12–20 ] To improve the device reliability, the recent trend for fl ash memory devices is to store information in discrete charge trapping sites such as in silicon nitride [ 17–20 ] or metal nanoparticles. [ 21–29 ] Recently, we reported that ordered arrays of metallic nanoparticles obtained by a micellar route and multilayered metallic nanoparticles can be used as charge storage media for non-volatile memory devices with tailored performances. [ 27–29 ] However, most of the research on nanoparticle-based memory devices has focused on binary data storage in the charge trapping layer. In this work, multiple data storage memory devices based on the controlled capacitive coupling of trapped electrons operated at room temperature have been fabricated by using highly ordered arrays of metal nanoparticles as the charge trapping elements. We present results from metal nanoparticle-based memory devices with controlled nanoparticle charge trapping elements, which undergo gate-voltage-adjustable multilevel memory states. Experimental and theoretical analysis of multilevel data manipulations and visualization of memory states has been done on the nanometer scale. Electrical multilevel data programming and data access of fi ve well-defi ned data levels were