Chang-seok Kang

A novel NAND-type MONOS memory using 63nm process technology for multi-gigabit flash EEPROMs

A NAND-type MONOS device has been successfully developed by breakthrough technologies including optimized cell structures and integration schemes providing favorable memory cell structures and peripheral circuits. In this study, optimized TANOS (TaN-Al2O 3-nitride-oxide- silicon) cells integrated using 63nm NAND flash technology showed high performance compatible to floating-gate (FG) cell. The newly-developed TANOS-NAND flash technology proved to be a promising candidate to replace FG memory beyond 50nm technology

Thermally robust Ta/sub 2/O/sub 5/ capacitor for the 256-Mbit DRAM

The thermal degradation of the Ta/sub 2/ O/sub 5/ capacitor during BPSG reflow has been studied. The cause of deterioration of Ta/sub 2/O/sub 5/ with the TiN top electrode was found to be the oxidation of TiN. By placing a poly-Si layer between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850/spl deg/C. The Ta/sub 2/O/sub 5/ capacitor with the TiN/poly-Si top electrode was integrated into 256-Mbit DRAM cells and excellent leakage current characteristics were obtained.

Highly Manufacturable 32Gb Multi -- Level NAND Flash Memory with 0.0098 μm 2 Cell Size using TANOS(Si - Oxide - Al2O3 - TaN) Cell Technology

A highly manufacturable 32Gb multi-level NAND flash memory with 0.0098 μm2 cell size using 40nm TANOS cell technologies has been successfully developed for the first time. The main key technologies of 40nm 32Gb NAND flash are advanced high N.A immersion photolithography with off-axis illumination system, advanced blocking oxide of the TANOS cell, and PVD tungsten and flowable oxide for bit line

Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure

The symmetric inversion-type S/D structure has been employed for achieving available program disturbance for scaled NAND flash memory beyond sub-40 nm node. The inversion S/D structure enables the channel doping to be reduced due to non-existence of n-lateral diffusion and it suppresses charge sharing between program-inhibit channels, resulting in superior program disturbance. Moreover, the cells show better current drivability in the technology node less than 50 nm by more successful working of gate fringing field with smaller word-line gap, compared to those with the n-diffused S/D junction.

Effects of Lateral Charge Spreading on the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory

It was found that the charge loss behavior of TANOS (TaN-Al2O3-nitride-oxide-silicon) cells for NAND flash memory application is highly dependent on the gate structures for the first time. The gate structures with trap layers remained on source and drain regions showed increased charge loss compared to the one with trap layers separated between different gate lines. The improvement by removing the trap layers between gate lines suggests that the lateral charge spreading via trap layers from the programmed cells to the adjacent erased cells contributes to the charge loss of the TANOS cells.

Multi-Level NAND Flash Memory with 63 nm-Node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure

For the first time, multi-level NAND flash memories with a 63 nm design rule are developed successfully using charge trapping memory cells of Si/SiO2/SiN/Al2O3/TaN (TANOS). We successfully integrated TANOS cells into multi-gigabit multi-level NAND flash memory without changing the memory window and circuit design of the conventional floating-gate type NAND flash memories by improving erase speed. The evolved TANOS cells show four-level cell distribution which is free from program disturbance and a charge loss of less than 0.4 V at high temperature bake test

A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond

A new 64-cell NAND flash memory with asymmetric S/D (Source/Drain) structure for sub-40nm node technology and beyond has been successfully developed. To suppress short channel effect in NAND memory cell, asymmetric S/D consisting of optimized junction and inversion layer induced by fringe field of WL bias which is applied at NAND operation conditions is successfully utilized. 64-cell NAND string which is double number of cells used in current NAND string is also used to further reduce bit cost by achieving over 10% chip size reduction while almost maintaining MLC (multi-level-cell) NAND performance requirements

Data Retention Characteristics of Nitride-Based Charge Trap Memory Devices with High-

The data retention characteristics of nitride-based charge trap memories using metal–oxide–nitride–oxide–silicon (MONOS) structures employing high-k dielectrics and high-work-function metal gates have been investigated. The fabricated MONOS devices with structures of TaN/Al2O3/Si3N4/SiO2/ p-Si show fast program/erase characteristics with a large memory window of greater than 6 V at program and erase voltages of ±18 V. From a bake retention test at high temperatures (200, 225, 250, and 275 °C), it is expected to take more than 40 years to lose less than 0.5 V charge loss at 85 °C. In this paper, we present an optimized cell structure for both improved data retention and erase speed, as well as a systematic study on the charge decay process in MONOS-type flash memory for high-density device applications.

k

To realize TANOS-NAND flash memory, key requirements like program/erase speed, read retention, and program disturb window should be satisfied. In this work, we present 63 nm NAND-type TANOS cells to satisfy all the requirements and to replace floating-gate cells in conventional NAND flash memory without changing a circuit design and a sensing window

Dielectrics and High-Work-Function Metal Gates for Multi-Gigabit Flash Memory

In the proposed new scheme, which is named self aligned trap-shallow trench isolation (SAT-STI), such process damage on high-k layer can be minimized, achieving the goal of isolating the storage nitride layer successfully.