Jani K. Jarvenhaara

A 3.6-to-1.8-V Cascode Buck Converter With a Stacked

This brief presents the analysis, design, and measurements of an integrated synchronous cascode dc-dc buck converter in 65-nm CMOS. Guidelines for optimal design of each thick-oxide device in the switch bridge are derived in order to obtain enhanced power efficiency. The form factor is improved by stacking the high-Q inductor and other converter components. The circuit shows a measured efficiency of 67.9% when converting 3.6 to 1.8 V at a switching frequency of 120 MHz and a load current of 140 mA. The efficiency enhancement factor of +26.4% is among the highest for integrated buck converters.

LC

The application of time-varying root-locus (TVRL) algorithm for transient analysis of electronic circuits with potentially unstable operating points is presented. The TVRL algorithm calculates the dynamic movement of evolving characteristic equation roots by computing them at a sequence of time instants during the circuit transient. This TVRL indicates the existence of potentially unstable operating points. An LC-filter with Q-enhancement is used as example to demonstrate the dynamics of the circuit characteristic equation roots during power supply transient.

Filter in 65-nm CMOS

The paper proposes analytical definitions of moderate inversion and moderate saturation. These definitions are introduced considering two different series expansions for the function ln2(x). The expansions are “matched”: the upper limit for convergence of the first series and the lower limit for convergence of the second series define the border and transition from weak to moderate inversion/saturation. The moderate inversion/saturation corresponds to approximation of the function ln2(x) by a modified sum of two first terms of the second series. Then, the condition of inversion/saturation is defined by dominance of one term with respect to another. The condition of moderate inversion/saturation is a necessary step in transition from weak to strong inversion/saturation. The introduced definitions correspond to MOS transistor operation physics and eliminate discontinuity in this transition.

Determining potentially unstable operating points using time-varying root-locus

A novel and simple solution for adjusting dead time in high speed DC-DC converters is proposed. The usual dead time adjustment of DC-DC converters through feedback control has limited speed. For the high speed converters extra circuitry and delays in the feedback should be minimized. A 240MHz DC-DC converter with the presented dead time circuit is designed on low-voltage fast CMOS process.

On moderate inversion/saturation regions as approximations to “reconciliation” model

The paper demonstrates that the source follower is the core of such seemingly disparate circuits as the wideband amplifier, crystal oscillator and emitter-coupled multivibrator. It is shown that the input impedance of the follower loaded by a capacitor has a negative real part. This part compensates partially or completely the resistive component of the signal source impedance. The compensation develops a strong overshoot in the step-signal transmission; in case of inductive component in the source impedance the circuit may operate as well as oscillator. The oscillators can be also obtained coupling two source followers; this may result in new oscillator circuits.

High Speed DC-DC Dead Time Architecture

This letter presents a method for optimum selection of synchronous buck converter switch bridge topology and devices in the CMOS technology of choice. The comparative method targets maximum power efficiency, and it assumes an application where the dc-dc converter is on the same IC as the load with a known constant operating point. As its principal idea, the method circumvents the need for exhaustive comparative simulation work to cover the vast design space of available MOS device and cascode/noncascode topology combinations. Instead, the method narrows the space by using a set of basic parameters to approximate the best combination. The result, thus, provides sharp focus for subsequent detailed design and topology-dependent optimization. The method is illustrated by comparing its results to simulations of synchronous 3.31.65-V buck converters in 45 and 65-nm CMOS with core, I/O, and high-voltage devices.

Source follower: A misunderstood humble circuit

The paper considers a new push-pull RC-oscillator/multivibrator. In the sinusoidal regime the circuit develops two counter-phase oscillations located at different DC levels. The DC level of the first oscillation is close to the power supply level, the DC level of the second oscillation is close to the ground. The transition from sinusoidal oscillations to the relaxation ones is achieved by changing the value of the capacitor present in the circuit, so that for small values of this capacitor the oscillations are sinusoidal; for large values the circuit develops relaxation oscillations. This transition is similar to that which exists in source-coupled oscillators/multivibrators. Indeed, this new oscillator may be considered as a version of source-coupled multivibrator using complementary gain stages.

A Rapid Switch Bridge Selection Method for Fully Integrated DCDC Buck Converters

In this paper, a buck DC-DC converter is presented that is capable of operation under variable input battery voltage ranging from 3.5V to 6V. The proposed converter is based on a new design technique using an adaptive biasing circuit for cascode power stage. The biasing circuit changes its configuration when the battery voltage drops down to 4.5V. The converter is implemented in 45-nm CMOS technology; it was simulated and its operation was verified at an output power of 200mW where it achieves a maximum power conversion efficiency of 81% for an output voltage of 1.25V.

Push-pull RC-oscillator/multivibrator

The paper presents a self-oscillating DC-DC integrated converter which is operable in the frequency range of 200MHz-260MHz. The circuit includes a cascoded power stage, and an integrated transformer. The primary of the transformer provides the transmission of power to the converter load. The secondary provides the feedback signal to the gates of cascoded transistors in the power stage. The feedback circuit includes a duty cycle detector and a pulse-shaping circuit. A detailed analysis of duty cycle detector operation is given. The conditions for a smooth start-up are indicated as well. The circuit was designed and simulated for 45 nm CMOS technology, and the calculated parameters of the duty cycle detector are compared with that of the extracted from layout converter.

A variable battery supply dc-dc buck converter designed for 45 nm-CMOS technology

The paper presents a cascoded power stage with automatic dead time generation. The circuit is using the inter-transistor node voltages of the cascode configuration as feedback control signals to delay turning ON the power transistors. The circuit is designed as the output stage of a fully-integrated buck converter. The steady-state operation is described. The waveforms simulated on 45-nm CMOS process show that in steady-state operation the short-circuit path and body diode conductions are avoided while effective zero-voltage switching (ZVS) are provided both for ground and power supply line; the calculated dead times are in a good agreement with simulation results.