Kim B. Ostman

Novel VCO Architecture Using Series Above-IC FBAR and Parallel LC Resonance

A quasi-monolithic voltage-tunable film bulk acoustic resonator (FBAR) enhanced oscillator for 2.1 GHz in 0.25-mum SiGe BiCMOS technology is designed, fabricated, and evaluated. The narrow-band FBAR was built above the SiGe circuit through later Si post-processing steps. The oscillator is based on a two-transistor loop structure and uses two resonators, namely a parallel LC tank and an above-IC FBAR in its series-resonant mode. The improvement in phase noise performance is significant compared to a similar reference LC voltage-controlled oscillator (VCO), with the best phase noise being -144.1 dBc/Hz at an offset of 1 MHz and -149.6 dBc/Hz at 3 MHz. The architecture offers advantages in overcoming frequency tuning difficulties usually present when using high-Q resonators. Although the width of the tuning range comes at some cost on phase noise, the measured performance satisfies contemporary wireless standards such as GPS

Characteristics of LNA Operation in Direct Delta–Sigma Receivers

This brief analyzes the dual role and operation of the low noise amplifier (LNA) in the recently introduced direct delta-sigma receiver (DDSR). First, the LNA functions as a transconductor in an integrator stage, and in this role, we explore the effects of LNA output impedance on quantization noise shaping by the system. In the second role of a voltage preamplifier, we show how the closed-loop DDSR structure impacts LNA voltage gain and system noise. LNA and system properties are thus intertwined and lead to the need for careful codesign. The reliability of the utilized continuous-time DDSR approximation is verified by simulating a sample receiver model.

A 2.5-GHz Receiver Front-End With Q-Boosted Post-LNA N-Path Filtering in 40-nm CMOS

This paper presents the analysis, design, and measurements of a 2.5-GHz receiver front-end in a 40-nm CMOS technology. The front-end utilizes RLC-resonator quality factor (Q) boosting and four-phase N-path filtering to improve the blocker filtering capabilities of the low-noise amplifier (LNA). Systematic analysis is performed in order to obtain a thorough design approach. Particular attention is paid to the passive mixer switches in the RLC case, for which we show that minimum switch resistance does not provide best noise figure (NF), nor best relative blocker attenuation. Moreover, the N-path filter extends the stable operating region of a Q-boosted LNA, and adding a noisy Q-boosting circuit can actually improve the receiver NF in practical realizations. The experimental CMOS front-end is flip-chip packaged, and a parasitic-aware input matching method for the electrostatic-discharge-protected LNA is proposed, analyzed, and verified. In nominal operation, the programmable front-end achieves a measured gain of 39 dB, an NF of 3.5 dB, and an out-of-band input-referred third order intercept point of > 0 dBm, while consuming 48 mA from a 1.1-V supply.

A 3.6-to-1.8-V Cascode Buck Converter With a Stacked

This brief presents the analysis, design, and measurements of an integrated synchronous cascode dc-dc buck converter in 65-nm CMOS. Guidelines for optimal design of each thick-oxide device in the switch bridge are derived in order to obtain enhanced power efficiency. The form factor is improved by stacking the high-Q inductor and other converter components. The circuit shows a measured efficiency of 67.9% when converting 3.6 to 1.8 V at a switching frequency of 120 MHz and a load current of 140 mA. The efficiency enhancement factor of +26.4% is among the highest for integrated buck converters.

LC

RF-to-digital conversion is a recent approach to digital-intensive wireless receiver operation. Such converters often employ delta-sigma (ΔΣ) modulation to transcend the traditional divide between receiver RF front-ends and baseband analog-to-digital converters (ADC). Research on the direct delta-sigma receiver (DDSR) architecture is one example of the emergence of next-generation ΔΣ modulators. It embeds a direct conversion receiver front-end as part of a feedback-type ΔΣ modulator structure with an active loop filter, which extends ADC operation to RF and changes the role of the low-noise amplifier (LNA) and mixing stages. RF-to-digital converters thus merge the two formerly separate design domains, requiring a paradigm shift in both RF and ADC design methods. Accordingly, this paper uses the DDSR as an example to bridge the gap between RF and ADC design, by providing a systematic understanding of the role, modeling, and design strategy of the related complete RF front-end. Most importantly, the analysis produces new design equations that link analog RF stage properties to their continuous-time (CT) ΔΣ modulator coefficients, thus providing a useful circuit design tool.

Filter in 65-nm CMOS

This letter presents a method for optimum selection of synchronous buck converter switch bridge topology and devices in the CMOS technology of choice. The comparative method targets maximum power efficiency, and it assumes an application where the dc-dc converter is on the same IC as the load with a known constant operating point. As its principal idea, the method circumvents the need for exhaustive comparative simulation work to cover the vast design space of available MOS device and cascode/noncascode topology combinations. Instead, the method narrows the space by using a set of basic parameters to approximate the best combination. The result, thus, provides sharp focus for subsequent detailed design and topology-dependent optimization. The method is illustrated by comparing its results to simulations of synchronous 3.31.65-V buck converters in 45 and 65-nm CMOS with core, I/O, and high-voltage devices.

Next-Generation RF Front-End Design Methods for Direct

This paper presents a 2.5-GHz RF-to-digital converter implemented in a 40-nm CMOS technology. The architecture embeds a direct-conversion receiver RF front-end in a 1.5-bit continuous-time ΔΣ modulator loop. This allows simultaneous channel filtering and noise shaping that begins already in the RF stages. The implemented design pays particular attention to the frequency-translating interface at the LNA output, where a programmable impedance enables a tradeoff between receiver sensitivity and maximum SNDR. The receiver consumes 90 mW from 1.1 V, and achieves a state-of-the-art noise figure (NF) of 4.2 dB and 50-dB peak SNDR for a 15-MHz RF bandwidth.

\Delta\Sigma

This paper analyzes a tradeoff between noise figure, blocker filtering, and noise shaping that is inherent in the recently introduced direct delta-sigma receiver approach. It originates in the competing requirements imposed by the front-end low noise amplifier operating as a transconductor in an N-path GmC integrator and as a voltage pre-amplifier in a closed-loop radio-frequency front-end. A generic receiver model for evaluating the tradeoff is presented and verified through simulation. We then propose a design method for managing the tradeoff in light of receiver target specifications.

Receivers

Powered by TCPDF (www.tcpdf.org) This material is protected by copyright and other intellectual property rights, and duplication or sale of all or part of any of the repository collections is not permitted, except that material may be duplicated by you for your research use or educational purposes in electronic or print form. You must obtain permission for any other use. Electronic or print copies may not be offered, whether for sale or otherwise to anyone who is not an authorised user. Ul Haq, Faizan; Östman, Kim B.; Englund, Mikko; Stadius, Kari; Kosunen, Marko; Koli, Kimmo; Ryynänen, Jussi A common-gate common-source low noise amplifier based RF front end with selective input impedance matching for blocker-resilient receivers

A Rapid Switch Bridge Selection Method for Fully Integrated DCDC Buck Converters

This paper presents a wideband blocker-tolerant Direct ΔΣ receiver (DDSR). Blockers are attenuated through selective input impedance matching and optimized gain design. The created impedance profile provides low receiver input impedance at blocker frequencies, while at desired frequencies, the impedance is boosted to matched condition through an up-converted positive feedback from the DDSR output. Receiver is evaluated in a 28nm fully-depleted silicon-on-insulator CMOS process with total power consumption of 25mW at 1V supply voltage. The receiver is designed for configurable operation from 0.7–2.7GHz, a baseband bandwidth of 10MHz, demonstrates a maximum noise figure of 6.2dB, and achieves a peak SNDR of 53dB with an out-of-band 1dB input compression point of −11.5dBm at 100MHz offset.