Janne Roos

Comparison of reduced-order interconnect macromodels for time-domain simulation

A typical integrated-circuit model consists of nonlinear transistor models and large linear RLC networks describing the interconnects. During the last decade, various model-reduction algorithms have been developed for replacing each RLC network with an approximately equivalent, but much smaller, model. Since these reduced-order models are described in the frequency domain, they have to be linked to the transient analysis of the whole nonlinear circuit, which can be done by replacing these models with appropriate macromodels. In the interconnect literature, the actual macromodel realization, which has a great impact on the transient-simulation CPU time, is often overlooked. This paper presents a comprehensive comparison of nine reduced-order interconnect macromodels for time-domain simulation: the macromodels are reviewed, presented in a unified manner, and compared both theoretically and numerically. Since we have implemented all the nine macromodels into the APLAC circuit simulation and design tool, we are able to present a fair and meaningful CPU-time comparison.

PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits

This paper presents a robust partitioning-based model-order reduction (MOR) method, PartMOR, suitable for reduction of very large RLC circuits or RLC-circuit parts of a non-RLC circuit. The MOR is carried out on a partitioned circuit, which enables the use of low-order moments and macromodels of few elements, while still preserving good accuracy for the reduction. As the method produces a positive-valued, passive, and stable reduced-order RLC circuit (netlist-in-netlist-out), it can be used in conjunction with any standard analysis tool or circuit simulator without modification. It is shown that PartMOR achieves excellent reduction results in terms of accuracy and reduced CPU time for RLC, RC, and RL circuits.

Improving the convergence of combined Newton-Raphson and Gauss-Newton multilevel iteration method

During the last years, multilevel methods have been applied in parallel circuit simulation. However, aiding the convergence of multilevel methods has gained only a little notice. This paper presents a combined Newton-Raphson and Gauss-Newton (NRGN) multilevel method for parallel circuit simulation in a networked environment. The NRGN method is formulated such that convergence aiding methods can be effectively applied. The example simulations show that, especially with step-size adjusting methods, the NRGN method improves the convergence and thus the speed of parallel circuit simulation.

An efficient piecewise-linear DC analysis method for general non-linear circuits

The convergence problems of conventional DC analysis can be partly avoided by using piecewise-linear analysis. This paper proposes a piecewise-linear DC analysis method that can efficiently handle arbitrary couplings between non-linear circuit elements. Piecewise-linear modelling of the non-linear circuit elements is automatically performed during simulation, using simplicial subdivisions. The number of linear regions, and thereby iterations, is considerably reduced by combining the common parts of separate simplicial subdivisions. Due to these reasons and since the method is formulated with the commonly used modified nodal approach, it has been possible to implement the method in the general-purpose circuit simulator APLAC. The correct operation of the method is demonstrated with three examples. Copyright

Study and development of an efficient RC-in-RC-out MOR method

This paper outlines the study and development of an efficient RC-in-RC-out model-order reduction (MOR) method suitable for reduction of very large sized RC circuits or the RC circuit parts of a non-RC circuit. The MOR is carried out on a partitioned circuit, which enables the use of low-order moments and macromodels of few elements. This benefit translates to a typical 10-100 times faster simulation with only a minimal error. The performance of the MOR method is evaluated with simulations and compared with other MOR algorithms.

Development and comparison of reduced-order interconnect macromodels for time-domain simulation

As signal speeds grow and feature sizes shrink in digital VLSI circuits, there is an increasing need to correctly model the interconnects between transistors. Since the size of the resulting RLC-interconnect network can be huge, model-reduction algorithms have been developed for replacing the RLC networks with reduced-order frequency-domain models. This paper focuses on interfacing these frequency-domain representations with the time-domain simulation of the original nonlinear circuit. Three well-known reduced-order macromodels are briefly reviewed and two new ones are proposed. Comparisons between the simulation times and memory consumption of the various models are presented.A typical integrated-circuit model consists of nonlinear transistor models and large linear RLC networks describing the interconnects. During the last decade, various model-reduction algorithms have been developed for replacing each RLC network with an approximately equivalent, but much smaller, model. Since these reduced-order models are described in the frequency domain, they have to be linked to the transient analysis of the whole nonlinear circuit, which can be done by replacing these models with appropriate macromodels. In the interconnect literature, the actual macromodel realization, which has a great impact on the transient-simulation CPU time, is often overlooked. This paper presents a comprehensive comparison of nine reduced-order interconnect macromodels for time-domain simulation: the macromodels are reviewed, presented in a unified manner, and compared both theoretically and numerically. Since we have implemented all the nine macromodels into the APLAC circuit simulation and design tool, we are able to present a fair and meaningful CPU-time comparison.

Hierarchical Model-Order Reduction Flow

This paper presents a hierarchical model-order reduction (HMOR) flow, where the linear parts of a hierarchically defined circuits are divided into independently reducable subcircuits. The impact of the hierarchical structure and circuit partitioning on two MOR methods is discussed and some simulation results are presented.

Efficient Initialization of Artificial Neural Network Weights for Electrical Component Models

The modeling of RF/microwave components for computer-aided design is facing new challenges because of increasing operation frequencies, circuit complexity, integration density, and decreasing time to market. Recently, it has been shown that Artificial Neural Networks (ANNs) offer solutions to urgent modeling problems encountered with conventional numerical methods (e.g., 3-D EM simulation) and empirical models. Fast and accurate models based on ANNs have been created for a wide range of components [ZG00k], [PAR01]. The crucial part in ANN-based modeling is ANN training, that is, optimization of ANN weights with given measurements or, say, 3-D EM simulation data. In [TF97] several ANN weight-initialization methods were introduced and compared mainly by means of classification problems. It was shown how the choice of an initialization method influences the convergence of the optimization and the optimal initial weights are, by some means, determined by the measurement/simulation data set. However, weight-initialization methods have not previously been systematically evaluated for electrical component modeling problems and the nature of the problems — the functions to be approximated — differs significantly from, e.g., classification problems with discrete/Boolean input/target values. In this paper, three methods for an initialization of ANN weights are experimentally evaluated for electrical component modeling applications. The third method, a special modification of the second method, is not found in literature. The methods are evaluated with respect to average ANN training error, ANN test error, and ANN training CPU time. Also, the standard deviations of ANN training and test errors are calculated for robustness analysis of the methods.

Speed-up and performance evaluation of piecewise-linear DC analysis

The good convergence properties of piecewise-linear (PWL) DC analysis have been thoroughly discussed in many papers. This paper, in turn, concentrates on the speed of PWL DC analysis, where the boundary crossing of linear regions plays a crucial role. Fast methods are presented for performing the following boundary-crossing computations: LU-decomposition update, matrix-equation solution, boundary-crossing direction, and damping-factor determination. Special attention is given to those PWL DC analysis methods that perform PWL modelling of the non-linear components on the fly; an adaptive method is proposed for controlling the accuracy of PWL modelling and speeding up simulation. The computational efficiency of the accelerated PWL DC analysis is discussed and compared with that of conventional, Newton–Raphson iteration-based, DC analysis. Finally, the performance evaluation is completed with realistic simulation examples: it is demonstrated that the speed of the accelerated PWL DC analysis is comparable with that of the conventional DC analysis. Copyright

On Nonlinear Iteration Methods for DC Analysis of Industrial Circuits

Several iterative methods have been tested in nonlinear DC analysis of industrial electronic circuits.