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Dive into the research topics where Martti Valtonen is active.

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Featured researches published by Martti Valtonen.


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 2011

PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits

Pekka Miettinen; Mikko Honkala; Janne Roos; Martti Valtonen

This paper presents a robust partitioning-based model-order reduction (MOR) method, PartMOR, suitable for reduction of very large RLC circuits or RLC-circuit parts of a non-RLC circuit. The MOR is carried out on a partitioned circuit, which enables the use of low-order moments and macromodels of few elements, while still preserving good accuracy for the reduction. As the method produces a positive-valued, passive, and stable reduced-order RLC circuit (netlist-in-netlist-out), it can be used in conjunction with any standard analysis tool or circuit simulator without modification. It is shown that PartMOR achieves excellent reduction results in terms of accuracy and reduced CPU time for RLC, RC, and RL circuits.


International Journal of Circuit Theory and Applications | 1999

An efficient piecewise-linear DC analysis method for general non-linear circuits

Janne Roos; Martti Valtonen

The convergence problems of conventional DC analysis can be partly avoided by using piecewise-linear analysis. This paper proposes a piecewise-linear DC analysis method that can efficiently handle arbitrary couplings between non-linear circuit elements. Piecewise-linear modelling of the non-linear circuit elements is automatically performed during simulation, using simplicial subdivisions. The number of linear regions, and thereby iterations, is considerably reduced by combining the common parts of separate simplicial subdivisions. Due to these reasons and since the method is formulated with the commonly used modified nodal approach, it has been possible to implement the method in the general-purpose circuit simulator APLAC. The correct operation of the method is demonstrated with three examples. Copyright


international symposium on circuits and systems | 1988

Dispersive transmission line model for nonlinear time domain circuit analysis

Timo Veijola; Martti Valtonen

A dispersive transmission-line model for time-domain circuit analysis is presented. The model includes skin effect and dielectric-loss frequency dependence. The line is modeled using short nondispersive line sections separated by lossy lumped circuits. The loss circuit consists of a series impedance due to the skin effect losses and parallel admittance due to the dielectric losses. The model presented includes a powerful numerical implementation where the line is described externally as a two-port. Internally the model is composed of electrically decoupled sections, thus enabling parallel computation. A numerical example of a coaxial cable circuit is presented, comparing the results with those obtained by frequency-domain analysis and the FFT (fast Fourier transform).<<ETX>>


Archive | 2012

Improving Model-Order Reduction Methods by Singularity Exclusion

Pekka Miettinen; Mikko Honkala; Janne Roos; Martti Valtonen

This paper presents a novel stand-alone method for overcoming a singular system matrix in Model-Order Reduction (MOR) algorithms, which would otherwise foil successful algorithm operation and thus reduction. The basic idea of the method is to locate and identify the circuit areas that generate the singularities to the system matrix prior to MOR, and exclude these from the reduction. The method is applicable to any netlist-in–netlist-out type MOR method.


Archive | 2012

Partitioning-Based Reduction of Circuits with Mutual Inductances

Pekka Miettinen; Mikko Honkala; Janne Roos; Martti Valtonen

This paper describes a novel model-order reduction (MOR) method to reduce the number of mutual inductances in conjunction with a recently proposed MOR algorithm, PartMOR. As the method produces passive mutual inductances as a reduction realization, it extends the existing RLC-in–RLC-out PartMOR to a RLCM-in–RLCM-out MOR method. The method is verified and compared to a well-known MOR method with test simulations and is shown to produce good reduction results in terms of CPU speed-up and generated error.


international conference on electronics, circuits, and systems | 2012

Accessible approach to wideband matching

Anu Lehtovuori; Risto Valkonen; Martti Valtonen

Wideband matching is a prerequisite nowadays in almost all wireless communication devices. In circuit theory, the basis for matching is traditionally an optimal conjugate matching, but in practical wideband problems, the goal is a predetermined moderate level of mismatch over a maximum frequency band. In this paper, a new practically oriented approach to design a wideband matching circuit is presented. In the approach proposed, an arbitrary, frequency-dependent, real-life load impedance can be illustrated on the Smith chart and a solution is sought through optimization using a commercial circuit simulator. In particular, the versatility of the matching circuit topology is taken into account. The usefulness of this approach is demonstrated for a CCE antenna load which has a diverse and exceptional frequency dependence.


international symposium on circuits and systems | 1994

Small-signal analysis of nonideal switched-capacitor circuits

Hannu Jokinen; Martti Valtonen

An approximate analysis method of nonideal switched capacitor circuits is introduced. The method solves the time domain presentation in steady state as well as the frequency response for nonideal circuits. Circuits may be composed of all kinds of linear components and nonlinear transistor model can be used for the switches. An example is given to demonstrate that the proposed method is efficient enough to be used in practical circuit design. Simulation results show good agreement with those obtained by conventional slow transient analysis.<<ETX>>


european conference on circuit theory and design | 2009

Measurement-based equivalent circuit model for ferrite beads

Mikko Hulkkonen; Timo Veijola; Antti Kallio; Mikael Andersson; Martti Valtonen

An equivalent circuit simulation model for ferrite beads is presented. Linear and nonlinear lumped frequency-independent R, L and C circuit elements are used to model the DC-bias dependency of the frequency response. An optimization scheme has been developed to extract the nominal component values and the coefficients of the nonlinear functions from the measured small-signal frequency responses at 1MHz - 3GHz and at several bias currents. Both APLAC and ELDO models for ferrites from three manufacturers have been extracted.


International Journal of Circuit Theory and Applications | 2004

A new rule for MESFET gate charge division based on the energy conservation principle

Antti Kallio; Martti Valtonen

The energy conservation problem in the MESFET gate charge model is presented. The energy conservation requirement leads to symmetrical transcapacitances in contradiction to the commonly accepted approaches. The transcapacitance symmetry is completely independent of device symmetry. The resulting small-signal capacitances are reciprocal. Reciprocal capacitances are often considered charge non-conservative because they do not contain transcapacitances, but in this approach reciprocity is the result of transcapacitance symmetry and the charge conservation problem is avoided since the charge-based model includes the transcapacitances. A method for dividing the MESFET gate charge into gate-drain and gate-source portions based on the energy conservation rule is developed, and the method is applied to the well-known Statz gate charge as an example. Copyright


international conference on electronics, circuits, and systems | 2002

Implementation of piecewise-linear DC analysis in APLAC

Janne Roos; Martti Valtonen; Jarmo Virtanen

Recently, we have developed many extensions to the piecewise-linear (PWL) DC analysis method. In this paper, working solutions are proposed for filling the gap between the academically oriented method and real-world DC-simulation problems. Thanks to the solutions proposed, our PWL DC analysis method is, finally, general and efficient enough to be implemented in a general-purpose circuit simulator. This paper describes the APLAC implementation of our PWL DC analysis method. The method is combined with the conventional DC analysis method of APLAC in a robust and user-friendly manner. The operation of the APLAC implementation is demonstrated with simulation examples.

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Dive into the Martti Valtonen's collaboration.

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Janne Roos

Helsinki University of Technology

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Mikko Honkala

Helsinki University of Technology

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Timo Veijola

Helsinki University of Technology

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Hannu Jokinen

Helsinki University of Technology

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Jarmo Virtanen

Helsinki University of Technology

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Veikko Porra

Helsinki University of Technology

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Antti Kallio

Helsinki University of Technology

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Keijo Nikoskinen

Helsinki University of Technology

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