Jared J. Hou

Synthesis and characterizations of ternary InGaAs nanowires by a two-step growth method for high-performance electronic devices.

InAs nanowires have been extensively studied for high-speed and high-frequency electronics due to the low effective electron mass and corresponding high carrier mobility. However, further applications still suffer from the significant leakage current in InAs nanowire devices arising from the small electronic band gap. Here, we demonstrate the successful synthesis of ternary InGaAs nanowires in order to tackle this leakage issue utilizing the larger band gap material but at the same time not sacrificing the high electron mobility. In this work, we adapt a two-step growth method on amorphous SiO(2)/Si substrates which significantly reduces the kinked morphology and surface coating along the nanowires. The grown nanowires exhibit excellent crystallinity and uniform stoichiometric composition along the entire length of the nanowires. More importantly, the electrical properties of those nanowires are found to be remarkably impressive with I(ON)/I(OFF) ratio >10(5), field-effect mobility of ∼2700 cm(2)/(V·s), and ON current density of ∼0.9 mA/μm. These nanowires are then employed in the contact printing and achieve large-scale assembly of nanowire parallel arrays which further illustrate the potential for utilizing these high-performance nanowires on substrates for the fabrication of future integrated circuits.

Controllable p-n switching behaviors of GaAs nanowires via an interface effect.

Due to the extraordinary large surface-to-volume ratio, surface effects on semiconductor nanowires have been extensively investigated in recent years for various technological applications. Here, we present a facile interface trapping approach to alter electronic transport properties of GaAs nanowires as a function of diameter utilizing the acceptor-like defect states located between the intrinsic nanowire and its amorphous native oxide shell. Using a nanowire field-effect transistor (FET) device structure, p- to n-channel switching behaviors have been achieved with increasing NW diameters. Interestingly, this oxide interface is shown to induce a space-charge layer penetrating deep into the thin nanowire to deplete all electrons, leading to inversion and thus p-type conduction as compared to the thick and intrinsically n-type GaAs NWs. More generally, all of these might also be applicable to other nanowire material systems with similar interface trapping effects; therefore, careful device design considerations are required for achieving the optimal nanowire device performances.

Tunable Electronic Transport Properties of Metal-Cluster- Decorated III-V Nanowire Transistors

A metal-cluster-decoration approach is utilized to tailor electronic transport properties (e.g., threshold voltage) of III-V NWFETs through the modulation of free carriers in the NW channel via the deposition of different metal clusters with different work function. The versatility of this technique has been demonstrated through the fabrication of high-mobility enhancement-mode InAs NW parallel FETs as well as the construction of low-power InAs NW inverters.

Surface roughness induced electron mobility degradation in InAs nanowires

In this work, we present a study of the surface roughness dependent electron mobility in InAs nanowires grown by the nickel-catalyzed chemical vapor deposition method. These nanowires have good crystallinity, well-controlled surface morphology without any surface coating or tapering and an excellent peak field-effect mobility up to 15,000 cm(2) V(-1) s(-1) when configured into back-gated field-effect nanowire transistors. Detailed electrical characterizations reveal that the electron mobility degrades monotonically with increasing surface roughness and diameter scaling, while low-temperature measurements further decouple the effects of surface/interface traps and phonon scattering, highlighting the dominant impact of surface roughness scattering on the electron mobility for miniaturized and surface disordered nanowires. All these factors suggest that careful consideration of nanowire geometries and surface condition is required for designing devices with optimal performance.

Facile synthesis and growth mechanism of Ni-catalyzed GaAs nanowires on non-crystalline substrates

GaAs nanowires (NWs) have been extensively explored for next generation electronics, photonics and photovoltaics due to their direct bandgap and excellent carrier mobility. Typically, these NWs are grown epitaxially on crystalline substrates, which could limit potential applications requiring high growth yield to be printable or transferable on amorphous and flexible substrates. Here, utilizing Ni as a catalytic seed, we successfully demonstrate the synthesis of highly crystalline, stoichiometric and dense GaAs NWs on amorphous SiO(2) substrates. Notably, the NWs are found to grow via the vapor-solid-solid (VSS) mechanism with non-spherical NiGa catalytic tips and low defect densities while exhibiting a narrow distribution of diameter (21.0 ± 3.9 nm) uniformly along the entire length of the NW (>10 µm). The NWs are then configured into field-effect transistors showing impressive electrical characteristics with I(ON)/I(OFF) > 10(3), which further demonstrates the purity and crystal quality of NWs obtained with this simple synthesis technique, compared to the conventional MBE or MOCVD grown GaAs NWs.

GaAs nanowire Schottky barrier photovoltaics utilizing Au–Ga alloy catalytic tips

Single GaAs nanowire photovoltaic devices were fabricated utilizing rectifying junctions in the Au–Ga catalytic tip/nanowire contact interface. Current-voltage measurements were performed under simulated Air Mass 1.5 global illumination with the best performance delivering an overall energy conversion efficiency of ∼2.8% for a nanowire of 70 nm in diameter. As compared with metal contacts directly deposited on top of the nanowire, this nanoscale contact is found to alleviate the well-known Fermi-level pinning to achieve effective formation of Schottky barrier responsible for the superior photovoltaic response. All these illustrate the potency of these versatile nanoscale contact configurations for future technological device applications.

Diameter dependence of electron mobility in InGaAs nanowires

In this work, we present the diameter dependent electron mobility study of InGaAs nanowires (NWs) grown by gold-catalyzed vapor transport method. These single crystalline nanowires have an In-rich stoichiometry (i.e., In0.7Ga0.3As) with dispersed diameters from 15 to 55 nm. The current-voltage behaviors of fabricated nanowire field-effect transistors reveal that the aggressive scaling of nanowire diameter will induce a degradation of electron mobility, while low-temperature measurements further decouple the effects of surface/interface traps and phonon scattering, highlighting the impact of surface roughness scattering on the electron mobility. This work suggests a careful design consideration of nanowire dimension is required for achieving the optimal device performances.

Stoichiometric Effect on Electrical, Optical, and Structural Properties of Composition-Tunable InxGa1–xAs Nanowires

Ternary InGaAs nanowires have recently attracted extensive attention due to their superior electron mobility as well as the ability to tune the band gap for technological applications ranging from high-performance electronics to high-efficiency photovoltaics. However, due to the difficulties in synthesis, there are still considerable challenges to assess the correlation among electrical, optical, and structural properties of this material system across the entire range of compositions. Here, utilizing a simple two-step growth method, we demonstrate the successful synthesis of composition and band gap tunable In(x)Ga(1-x)As alloy nanowires (average diameter = 25-30 nm) by manipulating the source powder mixture ratio and growth parameters. The lattice constants of each NW composition have been well correlated with the chemical stoichiometry and confirmed by high-resolution transmission electron microscopy and X-ray diffraction. Importantly, the as-grown NWs exhibit well-controlled surface morphology and low defect concentration without any phase segregation in all stoichiometric compositions. Moreover, it is found that the electrical nanowire device performances such as the turn-off and I(ON)/I(OFF) ratios are improved when the In concentration decreases at a cost of mobility degradation. More generally, this work suggests that a careful stoichiometric design is required for achieving optimal nanowire device performances.

Crystal phase and growth orientation dependence of GaAs nanowires on NixGay seeds via vapor-solid-solid mechanism

One of the challenges to utilize high performance III-V compound semiconductor nanowires (NWs) for large-scale technological applications is to control the crystal phase and growth orientation for homogenous nanowire properties. Here, we report the dependence of crystal structure and growth orientation of GaAs NWs on NixGay seeds via vapor-solid-solid mechanism. The crystal structure of catalytic seeds is found to direct the crystal phase of NWs with cubic NiGa seeds yielding zincblende GaAs NWs while hexagonal Ni2Ga3 seeds producing wurtzite GaAs NWs. Furthermore, the seed/nanowire interface plane relationship would dictate the epitaxial growth orientation of NWs, which is independent of the NW diameters and growth conditions. All these suggest the importance of well-controlled phase and orientation of catalysts for the synthesis of homogenous nanowires.

III–V nanowires: synthesis, property manipulations, and device applications

III–V semiconductor nanowire (NW) materials possess a combination of fascinating properties, including their tunable direct bandgap, high carrier mobility, excellent mechanical flexibility, and extraordinarily large surface-to-volume ratio, making them superior candidates for next generation electronics, photonics, and sensors, even possibly on flexible substrates. Understanding the synthesis, property manipulation, and device integration of these III–V NW materials is therefore crucial for their practical implementations. In this review, we present a comprehensive overview of the recent development in III–V NWs with the focus on their cost-effective synthesis, corresponding property control, and the relevant low-operating-power device applications. We will first introduce the synthesis methods and growth mechanisms of III–V NWs, emphasizing the low-cost solid-source chemical vapor deposition (SSCVD) technique, and then discuss the physical properties of III–V NWs with special attention on their dependences on several typical factors including the choice of catalysts, NW diameters, surface roughness, and surface decorations. After that, we present several different examples in the area of high-performance photovoltaics and low-power electronic circuit prototypes to further demonstrate the potential applications of these NW materials. Towards the end, we also make some remarks on the progress made and challenges remaining in the III–V NW research field.