Jason McNeely

Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop

In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch-sharing scheme to reduce the number of clocked transistors in the design. The newly proposed design also employs conditional discharge and split-path techniques to further reduce switching activity and short-circuit currents, respectively. As compared to the other state of the art double-edge triggered flip-flop designs, the newly proposed CBS_ip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively

Design of Sequential Elements for Low Power Clocking System

Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, we propose a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems.

Fast Motion Estimation System Using Dynamic Models for H.264/AVC Video Coding

H.264/AVC offers many coding tools for achieving high compression gains of up to 50% more than other standards. These tools dramatically increase the computational complexity of the block based motion estimation (BB-ME) which consumes up to 80% of the entire encoders computations. In this paper, computationally efficient accurate skipping models are proposed to speed up any BB-ME algorithm. First, an accurate initial search center (ISC) is decided using a smart prediction technique. Thereafter, a dynamic early stop search termination (DESST) is used to decide if the block at the ISC position can be considered as a best match candidate block or not. If the DESST algorithm fails, a less complex style of the motion estimation algorithm which incorporates dynamic padding window size technique will be used. Further reductions in computations are achieved by combining the following two techniques. First, a dynamic partial internal stop search technique which utilizes an accurate adaptive threshold model is exploited to skip the internal sum of absolute difference operations between the current and the candidate blocks. Second, a dynamic external stop search technique greatly reduces the unnecessary operations by skipping all the irrelevant blocks in the search area. The proposed techniques can be incorporated in any block matching motion estimation algorithm. Computational complexity reduction is reflected in the amount of savings in the motion estimation encoding time. The novelty of the proposed techniques comes from their superior saving in computations with an acceptable degradation in both peak signal-to-noise ratio (PSNR) and bit-rate compared to the state of the art and the recent motion estimation techniques. Simulation results using H.264/AVC reference software (JM 12.4) show up to 98% saving in motion estimation time using the proposed techniques compared to the conventional full search algorithm with a negligible degradation in the PSNR by approximately 0.05 dB and a small increase in the required bits per frame by only 2%. Experimental results also prove the effectiveness of the proposed techniques if they are incorporated with any fast BB-ME technique such as fast extended diamond enhanced predictive zonal search and predictive motion vector field adaptive search technique.

Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems

Clustered voltage scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the design of an efficient level converter with fewer power and delay overheads. In this paper, level-shifting flip-flop topologies are investigated. Different level-shifting schemes are analyzed and classified into groups: differential style, n-type metal-oxide-semiconductor (NMOS) pass-transistor style, and precharged style. An efficient level-shifting scheme, the clocked-pseudo-NMOS (CPN) level conversion scheme, is presented. One novel level conversion flip-flop (CPN-LCFF) is proposed, which combines the conditional discharge technique and pseudo-NMOS technique. In view of power and delay, the new CPN-LCFF outperforms previous LCFF by over 8% and 15.6%, respectively.

Multisensor Data Fusion Schemes for Wireless Sensor Networks

Data fusion systems is an active research field with applications in several fields such as manufacturing, surveillance, air traffic control, robotics and remote sensing. The wide interest in wireless sensor networks has fueled the interest in data fusion as a medium to compress and interpret the collected data from the spatially distributed sensors. The present paper gives a general overview on the current state of data fusion schemes for wireless sensor networks. Specifically this paper presents a review on some of the commonly used techniques such as Kalman filtering, beamforming, transferable belief model, filter-based techniques and linear mean square estimator.

An Efficient Data Reuse Motion Estimation Engine

We present a novel motion estimation engine (MEE) architecture that efficiently reuses search area data while fully utilizing the hardware resources. A 2-D processing element (PE) core is central to the architecture. Search area data flows both horizontally as well as vertically while the current block data is stationary. A clever PE design ensures simple but highly regular dataflow through the core avoiding long interconnect delays. For a search range of [-16,+15] and block size of 16, our architecture can perform motion estimation for 60 fps of 4CIF video at 100 MHz

A Low Power Domino with Differential-Controlled-Keeper

Domino circuits are used to achieve higher system performance than static CMOS techniques. This work briefly surveys domino keeper designs for high fan-in domino circuits. A new domino circuit structure is shown in this paper that reduces the power-delay-product over 16% as compared to previous domino techniques with keepers

A generalized fast motion estimation algorithm using external and internal stop search techniques for H.264 video coding standard

In this paper, a set of computationally efficient accurate skipping techniques are proposed for motion estimation. First, a partial internal stop search (ISS) technique which utilizes an accurate adaptive threshold model is exploited to skip the internal SAD (sum of absolute difference) operations between the current and reference blocks. Second, an external stop search (ESS) technique greatly reduces the unnecessary operations by skipping all the irrelevant blocks in the search area. The proposed techniques can be incorporated in any block matching motion estimation algorithm. Computational complexity reduction is reflected on the amount of saving in motion estimation encoding time. Simulation results using H.264 reference software (JM 12.4) show up to 71.26% saving in motion estimation time using the proposed techniques compared to the fast full search algorithm adopted in JM 12.4 with a negligible degradation in the PSNR by approximately 0.03 dB and a small increase in the required bits per frame by only 2%.

Low Power Design of Double-Edge Triggered Flip-Flop by Reducing the Number of Clocked Transistors

In this paper, a new technique for implementing low energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch shared (CBS) scheme to reduce the number of clocked transistors in the design. As compared to the other state of the art double-edge triggered flip- flop designs, the newly proposed CBSip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively.

“Voodoo” error prediction for bit-depth scalable video coding

A new prediction method for bit-depth scalable video coding is proposed in this paper. Correlation between the dropped bits during linear scaling tone mapping is used as the basis for using the error as an additional aid in predicting the high bit-depth enhancement layer. The residual to be transmitted in the enhancement layer is reduced by this technique. The effectiveness of this technique is increased when using a small quantization parameter. We show up to a 20% reduction in bit rate of the CAVLC output in our simulation test frames. Bit-depth scalability may be needed in future systems that will support legacy display applications as well as future high dynamic range displays.