Peiyi Zhao

High-performance and low-power conditional discharge flip-flop

In this paper, high-performance flip-flops are analyzed and classified into two categories: the conditional precharge and the conditional capture technologies. This classification is based on how to prevent or reduce the redundant internal switching activities. A new flip-flop is introduced: the conditional discharge flip-flop (CDFF). It is based on a new technology, known as the conditional discharge technology. This CDFF not only reduces the internal switching activities, but also generates less glitches at the output, while maintaining the negative setup time and small D-to-Q delay characteristics. With a data-switching activity of 37.5%, the proposed flip-flop can save up to 39% of the energy with the same speed as that for the fastest pulsed flip-flops.

Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop

In this paper, a new technique for implementing low-energy double-edge triggered flip-flops is introduced. The new technique employs a clock branch-sharing scheme to reduce the number of clocked transistors in the design. The newly proposed design also employs conditional discharge and split-path techniques to further reduce switching activity and short-circuit currents, respectively. As compared to the other state of the art double-edge triggered flip-flop designs, the newly proposed CBS_ip design has an improvement of up to 20% and 12.4% in view of power consumption and PDP, respectively

Design of Sequential Elements for Low Power Clocking System

Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, we propose a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems.

Low power and high speed explicit-pulsed flip-flops

Flip-flops play an important role in building digital CMOS designs. Their design and optimization is critical for high-performance and low power systems. In this paper, we propose high-performance and low power flip-flops based on the explicit-pulsed flip-flop (EPFF). These new flip-flops eliminate the hazardous glitches associated with the original EPFF output. The Static-EPFF (SEPFF) is developed for low-power dissipation purposes; it reduces the power dissipation by 13.9%-15.7%, and it enhances the speed by 4.86%-7.87%. For high-speed objectives, the dual path single-transistor-clocked EPFF (STC-EPFF) achieves 21% enhancement in speed over EPFF at the expense of increased power dissipation (12%).

Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems

Clustered voltage scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the design of an efficient level converter with fewer power and delay overheads. In this paper, level-shifting flip-flop topologies are investigated. Different level-shifting schemes are analyzed and classified into groups: differential style, n-type metal-oxide-semiconductor (NMOS) pass-transistor style, and precharged style. An efficient level-shifting scheme, the clocked-pseudo-NMOS (CPN) level conversion scheme, is presented. One novel level conversion flip-flop (CPN-LCFF) is proposed, which combines the conditional discharge technique and pseudo-NMOS technique. In view of power and delay, the new CPN-LCFF outperforms previous LCFF by over 8% and 15.6%, respectively.

Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits

As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented.

Design Asynchronous Circuits for Soft Error Tolerance

This paper presents a quasi delay insensitive (QDI) asynchronous circuit design paradigm -modified Null Convention Logic (NCL), for high single event upset (SEU) tolerance We investigate the behavior of the QDI circuit in the presence of SEUs, and propose a framework to evaluate the SEU sensitivity of the circuit. The modified NCL circuit can eliminate all SEUs in computational blocks if these SEUs occur when the computational blocks are in steady sates. Finally we present a case study of a two-bit adder.

A Low Power Domino with Differential-Controlled-Keeper

Domino circuits are used to achieve higher system performance than static CMOS techniques. This work briefly surveys domino keeper designs for high fan-in domino circuits. A new domino circuit structure is shown in this paper that reduces the power-delay-product over 16% as compared to previous domino techniques with keepers

Soft Error Hardening for Asynchronous Circuits

As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of Null Convention Logic circuits in the presence of particle strikes, and propose a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a normal energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented.

Contention reduced/conditional discharge flip-flops for level conversion in CVS systems

Clustered Voltage Scaling (CVS) is an effective way to decrease power dissipation. One of the design challenges is the efficient level converter with fewer overheads in power and delay. Several novel level conversion flip-flops (LCFF) are proposed: a single-ended contention reduced LCFF (CR-LCFF) and double-ended conditional discharge LCFFs (CD-LCFF). Novel circuit techniques are employed for reducing the LCFF overhead, including conditional discharge technique which effectively suppresses dynamic power, contention reduce technique which suppresses short circuit power in DCVSL circuits during transition. A new pulse generator with 10 transistors is used in the proposed LCFFs. In view of PDP, the new LCFFs outperform previous published designs by about 37.7%-41%.