Jaume Segura

Quiescent current analysis and experimentation of defective CMOS circuits

Physical defects widely encountered in todays CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. These models are used to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter. The results are compared with experimental data of integrated circuits fabricated with intentional defects. The influence of the characteristics of each defect on IDDQ has been investigated by electrical simulation and experimentation.

An approach to dynamic power consumption current testing of CMOS ICs

I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can be also detected. However, an important set of open and parametric defects escape quiescent power supply current testing because they prevent current elevation. Extending the consumption current testing time, from the static period to the dynamic one (i.e. considering the transient current), defects not covered with I/sub DDQ/ can be detected. Simulations using an on-chip sensor show that this technique can reach a high coverage for defects preventing current and also for those raising the static power consumption.

Approach to the analysis of gate oxide shorts in CMOS digital circuits

Abstract Although many integrated circuit processing or in-field defects change the functional behaviour of the circuit and may be detected by classical testing techniques, small spot and break defects in the active area of the transistors may just cause electrical parameter changes. In our work, experimental results are presented in order to characterize the behaviour of a class of such faulty devices. A fault model for gate oxide shorts is presented and used to analyse the conditions under which a typical CMOS inverter becomes functionally faulty. Static current inspection testing technique is considered for this kind of fault, proposing a static current circuit checker.

A modern look at the CMOS stuck-open fault

The stuck-open fault (SOF) is a difficult, hard failure mechanism unique to CMOS technology [1–3]. Its detection requires a specific 2-vector pair that examines each transistor in the logic gate for an open defect in its drain and/or source. This defect defies a guaranteed 100% detection. We will show that this mostly discarded failure mechanism is very relevant to modern ICs. Current leakage in nanoscale technologies influence significantly the behavior of this fault.

Soft error rate comparison of 6T and 8T SRAM ICs using mono-energetic proton and neutron irradiation sources

Abstract We present experimental results of soft errors produced by proton and neutron irradiation of minimum-size six-transistors (6T) and eight-transistors (8T) bit-cells SRAM memories produced with 65xa0nm CMOS technology using an 18xa0MeV proton beam and a neutron beam of 4.3–8.5xa0MeV. All experiments have been carried out at the National Center of Accelerators (CNA) in Seville, Spain. Similar soft error rate levels have been observed for both cell designs despite the larger area occupied by the 8T cells, although the trend for multiple events has been higher in 6T.

Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell

In this work we investigate the impact of the in height of FinFET transistors on the Soft Error Rate and Static Noise Margin of a FinFET-based SRAM cell. 3-D TCAD environment is used for the analysis. Results show that increases the fin height of FinFET transistors degrades the radiation robustness of the SRAM cell. However, increases the fin height of FinFET transistors improves the Static Noise Margin of the SRAM cell. This suggests that the optimum fin height value of FinFET transistor depends on the SRAM application.

MALDI-TOF analysis of blood serum proteome can predict the presence of monoclonal gammopathy of undetermined significance

Monoclonal gammopathy of undetermined significance (MGUS) is a plasma cell dyscrasia that can progress to malignant multiple myeloma (MM). Specific molecular biomarkers to classify the MGUS status and discriminate the initial asymptomatic phase of MM have not been identified. We examined the serum peptidome profile of MGUS patients and healthy volunteers using MALDI-TOF mass spectrometry and developed a predictive model for classifying serum samples. The predictive model was built using a support vector machine (SVM) supervised learning method tuned by applying a 20-fold cross-validation scheme. Predicting class labels in a blinded test set containing randomly selected MGUS and healthy control serum samples validated the model. The generalization performance of the predictive model was evaluated by a double cross-validation method that showed 88% average model accuracy, 89% average sensitivity and 86% average specificity. Our model, which classifies unknown serum samples as belonging to either MGUS patients or healthy individuals, can be applied to clinical diagnosis.

Analytical modeling of glitch propagation in nanometer ICs

We present a glitch propagation model that can be used to categorize the propagation likelihood of a given noise waveform trough a logic gate. This analysis is key to predict if a SET induced within a combinational block is capable of causing a SEU. The model predicts the glitch output characteristics given the input noise waveform for each gate in a 65- nm technology library. These noise transfer curves are fitted to known functions to have a simple analytical equation and compute the propagation. Comparison between simulations and model shows a good agreement.