Sebastiàn A. Bota

Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination

Memory design in the nanometer regime imposes specific restrictions to the cell layout structure requiring regular disposition of transistors to minimize the impact of process parameter variations. These layout restrictions invalidate many of the traditional design techniques oriented to improve cell immunity to radiation-induced events that, in turn, get worsened with technology scaling. We analyze two design alternatives to improve cell hardening compatible with regular cell layouts providing an extensive analysis to illustrate the benefits of each technique. One of the proposed solutions is based on transistor width modulation that provides an immunity enhancement at the cost of a moderate cell-size increase. The other solution is based on multithreshold voltage selection showing a moderate immunity improvement at the cost of no impact on the cell area. The combination of both techniques is shown to be optimum when considering other design metrics like static noise margin, read/write stability, access time, and leakage. Results are demonstrated on 90- and 65-nm commercial technologies.

Smart Temperature Sensor for Thermal Testing of Cell-Based ICs

In this paper we present a simple and efficient built-in temperature sensor for thermal monitoring of standard-cell based VLSI circuits. The proposed smart temperature sensor uses a ring-oscillator composed of complex gates instead of inverters to optimize their linearity. Simulation results from a 0.18-/spl mu/m CMOS technology show that the nonlinearity error of the sensor can be reduced when an adequate set of standard logic gates is selected.

Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs

The main contribution of this work is providing a static and dynamic enhancement of bit-cell stability for low-power SRAM in nanometer technologies. We consider a wide layout topology without bends in diffusion layers for the nanometer SRAM cell design to minimize the impact of process variations. The design restrictions imposed by such a nanometer SRAM cell design prevents from applying traditional read SNM improvement techniques. We use the SNM as a measure of the cell stability during read operations, and Qcrit to quantify the robustness against SEE during hold mode. The techniques proposed have a low impact on read time and leakage current while improving significantly the SNM. Moreover, the Word-line modulation technique has no impact on strategic cell parameters like area and leakage when in hold mode. Results obtained from both a commercial 65nm CMOS technology and a 45nm BPTM technology are provided.

Critical charge characterization in 6-T SRAMs during read mode

In this work we analyze the effects of radiation-induced transient pulses on 6T SRAM cells operating in read mode. The critical charge of a memory cell during read mode is lower than in hold mode. For 1 to 0 upsets, this reduction reaches a factor x1.5 for events produced by alpha particles; this factor is even higher for longer induced current pulses. The impact of events propagated through the bit-lines is also analyzed. Results show that it is possible the occurrence of an upset in the Sense Amplifier producing a wrong output in the readout process without changing the memory cell stored value.

Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs

As CMOS IC feature sizes shrink down to the nanometer regime, the need for more efficient test methods capable of dealing with new failure mechanisms increases. Advances in this domain require a detailed knowledge of these failure physical properties and the development of appropriated test methods. Several works have shown the relative increase of resistive defects (both opens and shorts), and that they mainly affect circuit timing rather than impacting its static DC behavior. Defect evolution, together with the increase of parameter variations, represents a serious challenge for traditional delay test methods based on fixed time delay limit setting. One alternative to deal with variation relies on adopting correlation where test limits for one parameter are settled based on its correspondence to other circuit variables. In particular, the correlation of circuit delay to reduced V DD has been proposed as a useful test method. In this work the authors investigate the merits of this technique for future technologies where variation is predicted to increase, analyzing the possibilities of detecting resistive shorts and opens

Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applications

Embedded SRAM yield dominates the overall ASIC yield, therefore the methodologies centered on improving SRAM cell stability will be introduced in the design as a mandatory. Word-line voltage modulation has showed that it is possible to improve cell stability during access operations. The high variability of physical and performance parameters introduce the need to adopt adaptable solutions to adequately improve SRAM cell stability. In this work, we present a wordline voltage selector circuit designed to modulate power-supply word-line voltage at each individual embedded SRAM block. The final area overhead is minimal and several strategies can be implemented with the embedded SRAM allowing adjust wordline voltage value during the life of ASIC, taking into account different operation, aging and degradations effects.

Low V/sub DD/ vs. delay: is it really a good correlation metric for nanometer ICs?

Delay testing at low- VDD has been proposed as a useful test method to expose delay defects not detectable at nominal supply voltages. The advantage of this technique comes from the reduced transistor strength at lower supply voltages that increases the impact of delay defects in faulty circuits with respect to the fault-free population. The correlation between the supply voltage and the delay, founded on the well-known relationship between these two circuit parameters, is used to set the delay limit according to each supply voltage value. Less attention has been given to the impact of supply voltage reduction on the circuit parameter variation dependency and its impact on the delay distribution. In this work we investigate this relationship showing that for a 130nm technology the delay variations are worsened when lowering the supply voltage from the nominal 1.2V to 0.9V by more than 80%. This dependence may question the advantage of Low-VDD vs. delay testing for future nanometer technologies

On-line write margin estimator to monitor performance degradation in SRAM cores

SRAM cell sensitivity to process variation increases aggressively with technology scaling trends. Long-term aging parameter variability degrades 6T-SRAM cells performance in the nanometre era. More accurate and non-invasive methodologies must be provided to extend the free-failure period for high reliability systems. This paper proposes a Word-Line Voltage Margin estimator to observe SRAM performance degradation. The proposed on-line estimator approach does not require memory array modification and it can be shared with all embedded memories in a SoC reducing its area overhead.

An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation

We present a STA tool based on a single-pass true path computation that efficiently determines the critical path list Given that it does not rely on a two-step process it can be programmed to find efficiently the N true paths from a circuit We also report and analyze the dependence of complex gates delay with the sensitization vector and its variation (that gets up to 15% in 6Snm technologies), and consider such effect in the path delay estimation Delay is computed from a simple polynomial analytical description that requires a one-time library parameter extraction process, making it highly scalable. Results on combinational ISCAS synthesized for three technologies (130nm, 90nm and 6Snm) provide better results in computation time, number of paths reported and delay estimation for these paths compared to a commercial tool.

Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories

Error correction codes combined with built-in current sensors (BICS) have been proposed as an effective technique to detect and correct SEU errors in memories. As technology scales down, multiple bit upsets affecting the same word are becoming more common as cell density increases. In this work we propose a Cross-BICS monitoring architecture to enhance SEU detection and correction in SRAM memories. The proposed architecture uses two types of BICS: one monitors the same-row cells (through power lines), while the other monitors the same–column cells (through bit lines).