Gabriel Torrens

Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination

Memory design in the nanometer regime imposes specific restrictions to the cell layout structure requiring regular disposition of transistors to minimize the impact of process parameter variations. These layout restrictions invalidate many of the traditional design techniques oriented to improve cell immunity to radiation-induced events that, in turn, get worsened with technology scaling. We analyze two design alternatives to improve cell hardening compatible with regular cell layouts providing an extensive analysis to illustrate the benefits of each technique. One of the proposed solutions is based on transistor width modulation that provides an immunity enhancement at the cost of a moderate cell-size increase. The other solution is based on multithreshold voltage selection showing a moderate immunity improvement at the cost of no impact on the cell area. The combination of both techniques is shown to be optimum when considering other design metrics like static noise margin, read/write stability, access time, and leakage. Results are demonstrated on 90- and 65-nm commercial technologies.

Static and dynamic stability improvement strategies for 6T CMOS low-power SRAMs

The main contribution of this work is providing a static and dynamic enhancement of bit-cell stability for low-power SRAM in nanometer technologies. We consider a wide layout topology without bends in diffusion layers for the nanometer SRAM cell design to minimize the impact of process variations. The design restrictions imposed by such a nanometer SRAM cell design prevents from applying traditional read SNM improvement techniques. We use the SNM as a measure of the cell stability during read operations, and Qcrit to quantify the robustness against SEE during hold mode. The techniques proposed have a low impact on read time and leakage current while improving significantly the SNM. Moreover, the Word-line modulation technique has no impact on strategic cell parameters like area and leakage when in hold mode. Results obtained from both a commercial 65nm CMOS technology and a 45nm BPTM technology are provided.

Critical charge characterization in 6-T SRAMs during read mode

In this work we analyze the effects of radiation-induced transient pulses on 6T SRAM cells operating in read mode. The critical charge of a memory cell during read mode is lower than in hold mode. For 1 to 0 upsets, this reduction reaches a factor x1.5 for events produced by alpha particles; this factor is even higher for longer induced current pulses. The impact of events propagated through the bit-lines is also analyzed. Results show that it is possible the occurrence of an upset in the Sense Amplifier producing a wrong output in the readout process without changing the memory cell stored value.

An Experimental Approach to Accurate Alpha-SER Modeling and Optimization Through Design Parameters in 6T SRAM Cells for Deep-Nanometer CMOS

We report a detailed analysis about the memory soft error rate (SER) dependence with transistor design parameters for six-transistor (6T) SRAM cells fabricated on a 65-nm CMOS commercial technology. SER data are obtained from accelerated test with an Am-241 alpha source. Five 6T cells with different nMOS and pMOS transistors size combinations were fabricated and characterized. After verifying that transistor width increase always provides higher critical charge values, SER data show that this value is improved only when increasing the pMOS transistors width. Memory cells containing non-minimum-width nMOS transistors always exhibit worse SER values than cells with minimum-size ones. In addition, one cell with a higher Qcrit than another can show a worse SER depending on the transistor type whose size is being enlarged. Accordingly to this, we have found that SER may be increased by 76% without modifying cell structure nor impacting cell area. This behavior is qualitatively and quantitatively explained through an analytical model that relates SER to Qcrit and the transistor design parameters.

Analysis of radiation-hardening techniques for 6T SRAMs with structured layouts

We analyze two complementary radiation-hardening techniques for 6T SRAM memories compatible with structured layouts. One approach relies on the individual selection of the threshold voltage of each of the four transistors forming the cross-coupled inverters of the SRAM cell. The other one is based on the modification of the widths of all pmos or all nmos transistors of the cell. The first technique does not affect the cell layout. The second one increases the minimum width of all pmos by a factor cp and the minimum width of all nmos by a factor cn. This prevents the formation of diffusion bends, allowing structured layouts. Both techniques provide an improvement in SEU robustness.

On-line write margin estimator to monitor performance degradation in SRAM cores

SRAM cell sensitivity to process variation increases aggressively with technology scaling trends. Long-term aging parameter variability degrades 6T-SRAM cells performance in the nanometre era. More accurate and non-invasive methodologies must be provided to extend the free-failure period for high reliability systems. This paper proposes a Word-Line Voltage Margin estimator to observe SRAM performance degradation. The proposed on-line estimator approach does not require memory array modification and it can be shared with all embedded memories in a SoC reducing its area overhead.

Pass-transistors pMOS based 8T SRAM cell for layout compaction

We present a new 8-transistor (8T) SRAM cell design that uses pMOS devices as cell pass transistors controlled by the write word-line signal. The main advantage of this schema is the composition of a balanced 8T SRAM cell having four nMOS and four pMOS transistor that enables a more compact layout and area reduction. An exhaustive analysis about the impact on key parameters such as leakage consumption, write and read stability margins, read delay time and single event upsets for the new cell is reported. A trade-off between cell area reduction and write noise margin improvement is observed, while the remaining parameters are not impacted.

Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories

Error correction codes combined with built-in current sensors (BICS) have been proposed as an effective technique to detect and correct SEU errors in memories. As technology scales down, multiple bit upsets affecting the same word are becoming more common as cell density increases. In this work we propose a Cross-BICS monitoring architecture to enhance SEU detection and correction in SRAM memories. The proposed architecture uses two types of BICS: one monitors the same-row cells (through power lines), while the other monitors the same–column cells (through bit lines).

Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation

SRAM cell stability analysis is typically based on Static Noise Margin (SNM) evaluation when in hold mode, although memory errors may also occur during read operations. Given that SNM varies with each cell operation, a thorough analysis of SNM in read mode is required. In this paper we investigate the SNM of OAM cells during write operations. The Word-Line Voltage modulation is proposed as an alternative to improve cell stability when in this mode. We show that it is possible to improve 8T OAM cells stability during write operations while reducing current leakage, as opposed to present methods that improve cell stability at the cost of leakage increase.

Evaluation of SRAM cell write margin metrics for lifetime monitoring of BTI-induced Vth drift

The Threshold voltage variability is increasing due to the process variability and reliability issues. SRAM cell stability dependence with threshold voltage is analyzed in order to extract reliability degradation due to BTI-induced Vth drift. The several write margin definitions are selected and their feasibility to be implemented in a threshold voltage built-in sensor is analyzed. The writability margins based on external cell nodes measurement have demonstrated best suitability for large memory arrays reducing the needs of hardware maintaining a good linearity for both high activity systems and long time storage.