Javad Ghasemi

Large-Area Semiconducting Graphene Nanomesh Tailored by Interferometric Lithography

Graphene nanostructures are attracting a great deal of interest because of newly emerging properties originating from quantum confinement effects. We report on using interferometric lithography to fabricate uniform, chip-scale, semiconducting graphene nanomesh (GNM) with sub-10 nm neck widths (smallest edge-to-edge distance between two nanoholes). This approach is based on fast, low-cost, and high-yield lithographic technologies and demonstrates the feasibility of cost-effective development of large-scale semiconducting graphene sheets and devices. The GNM is estimated to have a room temperature energy bandgap of ~30 meV. Raman studies showed that the G band of the GNM experiences a blue shift and broadening compared to pristine graphene, a change which was attributed to quantum confinement and localization effects. A single-layer GNM field effect transistor exhibited promising drive current of ~3.9 μA/μm and ON/OFF current ratios of ~35 at room temperature. The ON/OFF current ratio of the GNM-device displayed distinct temperature dependence with about 24-fold enhancement at 77 K.

Spatio-Temporal Bias-Tunable Readout Circuit for On-Chip Intelligent Image Processing

A new 96 × 96 array of 30 μm × 30 μm readout integrated circuit (ROIC) with an individual pixel tunable bias control is demonstrated. Detailed IC design, test structures, readout circuit building blocks, and applied techniques are discussed. The new ROIC is capable of providing a large voltage swing for the bias in both positive and negative polarities to each individual pixel, independently. These enhanced functionalities are achieved by modifying a capacitive transimpedance amplifier (CTIA) CMOS ROIC architecture. An FPGA-based test bench has also been developed to test and characterize the new ROIC system, for which software and hardware are described in detail. The test chip has been fabricated with 2P4M 0.35 μm high-voltage CMOS technology, where the bias voltage range is ±5 V and the output swing range is ±3.9 V. The demonstrated ROIC is an ideal infrastructure for implementation of region of interest enhancement and a solid base for infrared multispectral acquisition targeting an infrared retina.

A 6-m OOK VLC Link Using CMOS-Compatible p-n Photodiode and Red LED

This letter presents an ON-OFF-keying visiblelight-communication (VLC) link realized over 6-m distance. The transmitter is implemented with a commercially available red LED source at 650 nm. While most of the reported high-performance VLC links are using p-insulator-n photodetectors, this receiver employs a simple CMOS-compatible p-n photo-detector. A 150-Mb/s optical wireless transmission is measured with a bit-error rate of 1.3 × 10-6, which falls below the forward error correction limit of 3.8 × 10-3. The secondorder L-C-R equalization is used in both the transmitter and the receiver circuits to achieve maximum bandwidth extension. The VLC link is realized with a low illuminance of 250 lux. This power is below the common indoor illumination levels which enables advanced lighting-compatible VLC applications. The receiver and the source circuits consume around 240 and 105 mW, respectively, which represents to our knowledge a record energy-per-bit level of 2.3 nJ/b.

A novel blue-enhanced photodetector using honeycomb structure

In this paper, we present a honeycomb structure to maximize the edge-length in the detector and therefore enhance the detector responsivity in the blue region of the spectrum. A layout of a prototype honeycomb detector was designed and fabricated on a silicon wafer using a standard CMOS process. Based on our measured spectral response, the honeycomb structure improves the photocurrent in blue by about 60%. Moreover, the honeycomb detector demonstrates 20% less dark current than in conventional detector. Simulation results using MEDICI confirm the measured data.

A novel readout circuit for on-sensor multispectral classification

A new readout integrated circuit (ROIC) for multispectral classification is presented. The ROIC is designed to utilize the spectral response tunability of dot-in-a-well (DWELL) infrared photodetector to exploit the possibility of real-time on-chip multispectral imaging for classification in analog domain. The unit cells are designed to include all necessary elements needed for spectral classification, including high-voltage time-varying positive and negative biases, bipolar integration, and selective sample-and-hold circuits. A test chip was designed and fabricated using TSMCs 0.35 μm high-voltage technology. The test chip has successfully completed its initial functional tests and is ready for hybridization to a DWELL focal-plane array.

Spatio-temporal tunable pixels for multi-spectral infrared imagers

In this paper, a new 96 × 96 30 μm pitch mixed-signal readout integrated circuit (ROIC) with a pixel-level tunable bias control is demonstrated. The new ROIC is capable of providing a large bias voltage in both polarities on each individual pixel, independently. These enhanced functionalities are achieved by modifying a capacitive transimpedance amplifier (CTIA) CMOS ROIC architecture. In addition to the VLSI development, an FPGA-based testbench has been developed to test and characterize the new ROIC system. The unit cell consists of the CTIA integrator, two analog memories, one address selector, and one reference recover switch, built with 15 transistors and 3 capacitors. The test chip has been fabricated in 2P4M 0.35 μm high-voltage CMOS technology, where the bias voltage range is +/-5V and the output voltage swing is +/-3.9 V.

A meter-scale 600-Mb/s 2×2 imaging MIMO OOK VLC link using commercial LEDs and Si p-n photodiode array

This paper presents a free-space 4-channels imaging multiple-input multiple-output (MIMO) system for On-Off-Keying (OOK) Visible-Light-Communication (VLC) links. An aggregate data-rate of 600 Mb/s is measured over 6 meters link distance with a bit-error-rate (BER) below 10−3 with the 4-channels simultaneously modulated. While the majority of published VLC works to date use components-off-the-shelf (COTS) PIN or Avalanche PDs that require both non-standard and/or higher cost fabrication processes as well as high reverse bias potential, the presented receiver in this paper employs a 2×2 on-chip Nwell/Psub photodiodes (PD) array fabricated in a low cost CMOS-compatible process. To extract high data rate performance out of the proposed CMOS low speed PD array, a 2nd-order LCR equalization is used to compensate for the stringent bandwidth limitation of the PD, measured around 20 MHz and push the speed up to 150 Mbps/channel. With a red light-emitting-diode (LED) array at 650 nm, the 4-channels MIMO setup DC power consumption is 1.38 W, which represents to our knowledge an energy-per-bit record performance for OOK VLC systems of 2.3 nJ/bit.

A robust 2×2 CMOS receiver array for meter-scale point-to-point OOK VLC links

This paper presents a fully integrated 2×2 optical receiver array for Point-to-Point (P2P) On-Off-Keying (OOK) visible-light communication (VLC) links. The 2×2 PD-array design constraints and cross-talk issues are discussed. Each receiver exhibits a low input referred noise density of 5 pA/VHz to meet the sensitivity requirements of free-space optical wireless links in the visible spectrum. The VLC receiver is tested as a part of an optical setup at 2.7 m and 6.7 m distances from a 680-nm laser-diode source. A measured 2.3 Gb/s per-channel data-rate with a VLC-compliant bit-error-rate is achieved through the use of high bandwidth circuit design techniques and a programmable integrated equalizer function. The receiver is implemented in AMS 0.35 μm technology. Each single receiver draws 65 mA from a 3.3 V DC voltage supply. The complete array size is 2.0 mm × 1.6 mm.

CMOS approach to compressed-domain image acquisition

A hardware implementation of a real-time compressed-domain image acquisition system is demonstrated. The system performs front-end computational imaging, whereby the inner product between an image and an arbitrarily-specified mask is implemented in silicon. The acquisition system is based on an intelligent readout integrated circuit (iROIC) that is capable of providing independent bias voltages to individual detectors, which enables implementation of spatial multiplication with any prescribed mask through a bias-controlled response-modulation mechanism. The modulated pixels are summed up in the image grabber to generate the compressed samples, namely aperture-coded coefficients, of an image. A rigorous bias-selection algorithm is presented to the readout circuit, which exploits the bias-dependent nature of the imagers responsivity. Proven functionality of the hardware in transform coding compressed image acquisition, silicon-level compressive sampling, in pixel nonuniformity correction and hardware-level implementation of region-based enhancement is demonstrated.

Blue-enhanced and bandwidth-extended photodiode in standard 0.35-pm CMOS

In this paper, a photodiode structure based on N×N junctions is presented to enhance responsivity in the blue region and provide optical-bandwidth extension. The use of subsections or multiple junctions increases the number of generated blue photo-carriers as well as the collection speed of photo-carriers at the depletion regions edges. An NWell/Psub photodiode formed of 5×5 subsections is designed and fabricated in standard AMS 0.35 pm CMOS technology with the OPTO process option. The photodiode is compared to a solid structure with a single section having the same optical window area of 100 pm × 100 pm. A responsivity improvement of around 10% ∼ 15% is measured between 400 nm to 550 nm wavelength. The normalized AC-responsivity shows a 2× increase in bandwidth and at least 2 dB improvement around the cut-off frequency of the reference PD at 1 V reverse bias voltage.