Payman Zarkesh-Ha

Interconnect opportunities for gigascale integration

Throughout the past four decades, semiconductor technology has advanced at exponential rates in both productivity and performance. In recent years, multilevel interconnect networks have become the primary limit on the productivity, performance, energy dissipation, and signal integrity of gigascale integration. Consequently, a broad spectrum of novel solutions to the multifaceted interconnect problem must be explored. Here we review recent salient results of this exploration. Based upon prediction of the complete stochastic signal interconnect length distribution of a megacell, optimal reverse scaling of each pair of wiring levels provides a prime opportunity to minimize cell area, clock period, power dissipation, or number of wiring levels. Using a heterogeneous version of Rents rule, a design methodology for the global signal, clock, and power/ground distribution networks for a system-on-a-chip has been derived. Wiring area, bandwidth, and signal integrity are the prime constraints on the design of the networks. Three-dimensional integration offers the opportunity to reduce the length of the longest global interconnects in a distribution by as much as 75%. Wafer-level batch fabrication of chip input/output interconnects and chip scale packages provides new benefits such as I/O bandwidth enhancement, simultaneous switching-noise reduction, and lower cost of packaging and testing. Microphotonic interconnects have long-term potential to reduce latency, power dissipation, and crosstalk while increasing bandwidth.

Impact of three-dimensional architectures on interconnects in gigascale integration

An interconnect distribution model for homogeneous, three-dimensional (3-D) architectures with variable separation of strata is presented. Three-dimensional architectures offer an opportunity to reduce the length of the longest interconnects. The separation of strata has little impact on the length of interconnects but a large impact on the number of interstratal interconnects. Using a multilevel interconnect methodology for an ITRS 2005 100 nm ASIC, a two-strata architecture offers a 3.9/spl times/ increase in wire-limited clock frequency, an 84% decrease in wire-limited area or a 25% decrease in the number of metal levels required. In practice, however, such fabrication advances as improved alignment tolerances in wafer-bonding techniques are needed to gain key advantages stemming from 3-D architectures for homogeneous gigascale integrated circuits.

Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip

A system-on-a-chip (SoC) contains several pre-designed heterogeneous megacells that have been designed and routed optimally. In this paper a new stochastic net-length distribution for global interconnects in a nonhomogeneous SoC is derived using novel models for netlist, placement, and routing information. The netlist information is rigorously derived based on heterogeneous Rents rule, the placement information is modeled by assuming a random placement of terminals for a given net in a bounding area, and the routing information is constructed based on a new model for minimum rectilinear Steiner tree construction (MRST). The combination of the three models gives a priori estimation of global net-length distribution in a heterogeneous SoC. Unlike previous models that empirically relate the average length of the global wires to the chip area, the new distribution provides a complete and accurate distribution of net-length for global interconnects. Through comparison with actual product data, it is shown that the new stochastic model successfully predicts the global net-length distribution of a heterogeneous system.

Characterization and modeling of clock skew with process variations

A new compact model for on-chip clock skew as a function of device, interconnect, and system parameter variations is derived. Unlike previous models that describe qualitative behavior of clock skew components, the new model provides a closed form expression for each clock skew component. An example of clock skew components for a typical design using 0.18 /spl mu/m CMOS technology is investigated.

Global interconnect design in a three-dimensional system-on-a-chip

A stochastic model for the global net-length distribution of a three-dimensional system-on-a-chip (3D-SoC) is derived. Using the results of this model, a global interconnect design window for a 3D-SoC is established by evaluating the constraints of: 1) wiring area; 2) clock wiring bandwidth; and 3) crosstalk noise. This window elucidates the optimum 3D-SoC global interconnect parameters for minimum pitch, minimum aspect ratio, and maximum clock frequency. In comparison to a two-dimensional system-on-a-chip (2D-SoC), the design window expands for a 3D-SoC to allow greater flexibility of interconnect parameters, thus increasing the guardbands to process variations. In addition, the limit on the maximum global clock frequency is revealed to increase as S/sup 2/, where S is the number of strata. This increase in on-chip signaling rate, however, comes at the expense of I/O density, highlighting the need for new high-density-I/O packaging techniques to exploit the full potential of 3D-SoC.

A stochastic global net-length distribution for a three-dimensional system-on-a-chip (3D-SoC)

A global net-length distribution for three-dimensional system-on-a-chip architectures is derived to quantify the impact of the number of strata, or active layers, on the length of the long global interconnects. Model projections indicate a reduction in the global net length as the square root of the number of strata, thus enabling a significant reduction in chip footprint area, power dissipation, and global cycle time in comparison to a two-dimensional system-on-a-chip. Unlike its homogeneous counterpart, the vertical integration of a heterogeneous system is not limited by the density of interstratal interconnects. The size of the large megacells, especially memory, may restrict the effectiveness of a large number of strata.

A three-dimensional stochastic wire-length distribution for variable separation of strata

A complete wire-length distribution for future three-dimensional, homogeneous gigascale integrated (GSI) architectures with variable vertical separation of strata is derived. Because stratal pitch was not found to impact the wire-length distribution significantly, bonded three-dimensional implementations which are technologically feasible can be used to obtain large increases in global clock frequencies. The longest interconnect can be reduced by 30% through the introduction of a single additional stratum. A 93% reduction in the length of the longest interconnect can be obtained through the optimal use of a three-dimensional architecture for a 100 nm ASIC, potentially leading to a 15.8 times increase in global clock frequency.

Prediction of interconnect fan-out distribution using Rent's rule

Based on Rent’s rule, a well-established empirical relationship, a rigorous derivation of the interconnect fan-out distribution for random logic networks is performed. Through comparison with actual product data, it is shown that the model successfully predicts the fan-out distribution of a random logic network. Using the closed form expression for the fan-out distribution, its application to predict the global level netlist information in a system-on-a-chip is presented.

Interconnecting device opportunities for gigascale integration (GSI)

In recent years interconnecting devices have become primary limits on the performance, energy dissipation, signal integrity, and productivity of gigascale integration (GSI). Opportunities to address the interconnect problem include new materials and processes, reverse scaling, novel microarchitectures, three-dimensional integration, input/output interconnect enhancements, RF wireless interconnects and microphotonics.

A compact physical via blockage model

Via blockage due to signal interconnects and its impact on wirability of multi-billion-transistor chips are systematically analyzed. Via classifications are introduced. By taking advantage of a stochastic interconnect length distribution and a multi-level interconnect network architecture, a physical via blockage model exploiting channel availability is proposed. This model reveals that the most severe via blockage occurs on first metal level, wasting more than 10% and up to about 50% of wiring area. A new perspective on chip size limit imposed by via blockage is also provided by using the proposed model.