Mona Mostafa Hella

A 1.94 to 2.55 GHz, 3.6 to 4.77 GHz Tunable CMOS VCO Based on Double-Tuned, Double-Driven Coupled Resonators

This paper presents a multi-band CMOS VCO using a double-tuned, current-driven transformer load. The dual frequency range oscillator is based on enabling/disabling the driving current in the secondary port of the transformer. This approach eliminates the effect of switches connected directly to the VCO tank whose capacitance and on-resistance affect both the tuning range and the phase noise of a typical multi-band oscillator. The relation between the coupling coefficient of the transformer load, selection of frequency bands, and the resulting quality factor at each band is investigated. The concept is validated through measurement results from a prototype fabricated in 0.25 ¿m CMOS technology. The VCO has a measured tuning range of 1.94 to 2.55 GHz for the low frequency range and 3.6 to 4.77 GHz for the high frequency range. It draws a current of 1 mA from 1.8 V supply with a measured phase noise of -116 dBc/Hz at 1 MHz offset from a 2.55 GHz carrier. For the high frequency band, the VCO draws 10.1 mA from the same supply with a phase noise of -122.8 dBc/Hz at 1 MHz offset from a 4.77 GHz carrier.

Multi-transceiver optical wireless spherical structures for MANETs

Due to its high bandwidth spectrum, Free-Space-Optical (FSO) communication has the potential to bridge the capacity gap between backbone fiber links and mobile ad-hoc links, especially in the last-mile. Though FSO can solve the wireless capacity problem, it brings new challenges such as frequent disruption of wireless communication links (intermittent connectivity) and the line-of-sight (LOS) requirements. In this paper, we study a multi-transceiver spherical FSO structure as a basic building block for enabling optical spectrum in mobile ad-hoc networking. We outline optimal designs of such multi-transceiver subsystems such that coverage is maximized and crosstalk among neighboring transceivers is minimized. We propose a low-level packaging architecture capable of handling hundreds of transceivers on a single structure. We also present MANET transport performance over such multi-element mobile FSO structures in comparison to legacy RF-based MANETs.

Integrated High-Frequency Power Converters Based on GaAs pHEMT: Technology Characterization and Design Examples

The potential of GaAs pHEMT technology for high-frequency power-switching applications is discussed within the context of integrated power supplies for portable wireless systems. Various technology considerations are presented, including the optimization of the power-switching transistor and passives integration. Two design examples for integrated dc-dc converters are implemented in a 0.5-μm GaAs E/D pHEMT process. The first uses coupled inductors to reduce the current ripple and enhance the dynamic performance of the converter. The two-phase, 0.5 A/phase converter occupies 2 mm × 2.1 mm without the output network. An 8.7-nH filter coupled inductor is implemented in 65-μm-thick top copper metal layer, and flip-chip bonded to the dc-dc converter board. The presented converter converts 4.5-V input to 3.3-V output at 150-MHz switching frequency with a measured power efficiency of 84%, which is one of the highest efficiencies reported to date for similar current/voltage ratings. The second example is a hysteric controlled, 100-MHz switching frequency single-phase GaAs pHEMT buck converter designed to drive power amplifier loads. The design can deliver up to 37-dB·m output power and has a peak efficiency of 88% and a 3-dB bandwidth of 14.5 MHz.

Analysis and Optimization of Asynchronously Controlled Electrostatic Energy Harvesters

Mechanical to electrical energy conversion employing variable capacitors is assisted by electronic circuits that can have synchronous or asynchronous architectures. The later does not require synchronization of electrical events with mechanical motion, which eliminates difficulties in gate clocking and the power consumption associated with intelligent control circuitry. However, implementation of asynchronous energy harvesting circuits with the mechanical-to-electrical converter can be detrimental to the performance of the converter when done without concurrent optimization of the mechanical device and the circuit, an aspect mainly overlooked in the literature. This paper carries out system level analysis of electrostatic micro-generators with asynchronous control and charge fly-back mechanism to optimize the useful energy generated by the harvester. Our theoretical and experimental investigations show that there is an optimum value for either the storage capacitor or cycle number for maximum scavenging of ambient energy via asynchronous electrostatic transduction. The analysis also indicates that the maximum power is extracted from the system when approaching synchronization of mechanical and electrical events. However, there is a region of interest where the storage capacitor can be optimized to produce almost 70% of the ideal power, taken as the power harvested with synchronous converters when neglecting the power consumption associated with synchronizing control circuitry. Theoretical predictions are confirmed by measurements on an asynchronous energy harvesting circuit implemented with a macro-scale electrostatic converter prototype.

High speed photodiodes in standard nanometer scale CMOS technology: a comparative study

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

Localized microwave heating in microwells for parallel DNA amplification applications

This work explores the potential of microwave heating for applications requiring parallel DNA amplification platforms. Device characterization and thermal modeling is performed on 4.1μl microfluidic chamber fabricated in polycarbonate. Microwave power at 6GHz is delivered to the chamber via copper transmission line in a microstrip configuration. Microwave power reflection coefficient and temperature measurements are performed to characterize the power coupled to the chamber and rate of change in temperature. Temperatures up to 72°C are achieved with less than 400mW power applied at the input of the transmission line. Initial heating and cooling rates measured experimentally are ∼7 and ∼6°C∕s, respectively. These results suggest that microwave heating is an efficient, rapid heating technique suitable for programmable, parallel DNA amplification platforms to be empolyed in future genetic analysis systems.

A 60 GHz CMOS combined mm-wave VCO/divider with 10-GHz tuning range

This paper proposes the use of N-push operation for combining the functions of the VCO and dividers in the mm-wave frequency range. If employed in a PLL, the combined VCO/divider (C-VCO/D) would potentially provide wider tuning range than traditional mm-wave PLLs employing injection locked frequency dividers, thus exploiting the full range available in the 60GHz band (57GHz–64GHz). The C-VCO/D is fabricated in 130nm IBM CMOS technology and achieves a tuning range from 55GHz-65GHz using a VDD=1.5V, Icore=20mA, and Ibuffer=15mA. The C-VCO/D has a phase noise of 97.1 dBc/Hz at 1MHz Offset.

A 0.5-V 3.6/5.2 GHz CMOS multi-band LC VCO for ultra low-voltage wireless applications

In this paper, an ultra low-voltage multiband CMOS VCO based on tunable band-limited negative resistance approach is presented. The proposed technique eliminates the need for switching elements that are connected directly to the tank and limit the tuning range and phase noise performance. The oscillator draws a current of 6 mA from 0.5 V supply with a phase noise of -117 dBc/Hz at 1 MHz offset from 3.6 GHz carrier. For the high frequency band, it draws 4 mA from the same supply with a phase noise of -117 dBc/Hz at 1 MHz offset from 5.2 GHz.

Modeling Terahertz Plasmonic Si FETs With SPICE

As operating frequencies of Si FETs continue to grow, commercial circuit modeling tools must provide accurate simulations at very high frequencies with the ability to model plasmonic FETs in large and complex circuits. Traditional compact SPICE models used by commercial CAD tools model the channel resistance and capacitance and gate resistance as single lumped elements or use approximations to model the distributed nature of the FET channel. At high frequencies, these models become inaccurate and fail to model device physics properly. To describe plasmonic FETs, a THz SPICE model is developed for Si FETs. The THz SPICE model is validated experimentally to be in close agreement with measured results. The model is used to show predicted device response at different technology nodes.

A 150MHz, 84% efficiency, two phase interleaved DC-DC converter in AlGaAs/GaAs P-HEMT technology for integrated power amplifier modules

This paper presents a high efficiency, high switching speed, two-stage interleaved DC-DC buck converter with negatively-coupled inductors in AlGaAs/GaAs technology, targeting integrated power amplifier modules. The flip chip DC-DC converter is implemented in 0.5 µm GaAs pHEMT process and occupies 2 × 2.1mm2 without the output network. The inductors in the output network are implemented in 65 µm thick top copper metal layer and have a quality factor of 25 at 150 MHz. The interleaved DC-DC converter achieves 84% efficiency when operating at 150MHz switching frequency with 4.5V/3.3V conversion ratio and 1A load current.