Javier A. Salcedo

Design and integration of novel SCR-based devices for ESD protection in CMOS/BiCMOS technologies

Robust and novel devices called high-holding low-voltage trigger silicon controlled rectifiers (HH-LVTSCRs) for electrostatic discharge (ESD) protection of integrated circuits (ICs) are designed, fabricated and characterized. The S-type current-voltage (I-V) characteristics of the HH-LVTSCRs are adjustable to different operating conditions by changing the device dimensions and terminal interconnections. Comparison between complementary n- and p-type HH-LVTSCR devices shows that n-type devices perform better than p-type devices when a low holding voltage (V/sub H/) is allowed during the on-state of the ESD protection structure, but when a relatively high holding voltage is required, p-type devices perform better. Results further demonstrate that HH-LVTSCRs with a multiple-finger layout render high levels of ESD protection per unit area, applicable in the design of ICs with stringent ESD protection requirements of over 15 kV IEC.

A novel dual-polarity device with symmetrical/asymmetrical S-type I-V characteristics for ESD protection design

A novel and compact device with adjustable forward and reverse conductions and symmetrical/asymmetrical I-V characteristics for ESD (electrostatic discharge) applications is presented. The device allows for the dual-polarity conduction with the proper selection of blocking junction configurations. This design enables high-level ESD protections for various mixed-signal integrated circuits operating under a wide range of symmetrical and asymmetrical bias conditions.

On-chip protection for automotive integrated circuits robustness

On-chip protection architecture for automotive ICs (integrated circuits) system-level robustness is introduced. It comprises three-level protection for interface pins with high bidirectional voltage swing. A first protection stage is optimized to sustain the largest portion of the ESD (electrostatic discharge) and EMI (electromagnetic interference)-induced stress. A second-level protection stage is customized to sustain the relatively lower IC-level ESD stress, and the third level protection stage absorbs the initial transient voltage impulse.

Electrostatic discharge protection framework for mixed-signal high voltage CMOS applications

Electrostatic discharge (ESD) protection requirements for high voltage (HV) MOS technology are continuously evolving and increasingly stringent. To address the ever changing technology ESD constraints, a method for design, characterization, and integration of reliable mixed-signal HV MOS ESD solutions is introduced in this study. The dynamic response, design trade-offs and ESD verification in two HV CMOS-based technologies are discussed and depicted via fast transient and quasi-static measurements in the ESD-time domain.

Snapback and Postsnapback Saturation of Pseudomorphic High-Electron Mobility Transistor Subject to Transient Overstress

The snapback and postsnapback saturation characteristics in a pseudomorphic high-electron mobility transistor (PHEMT) subject to electrostatic discharge (ESD) transient overstress are studied. This is undertaken, for the first time, via transmission line pulsing (TLP)-like 2-D device simulations and benchmarked against TLP measurements. Physical mechanisms underlying the postsnapback behavior and ESD-induced failure are identified and discussed by analyzing TLP-like simulation results rather than extrapolating dc-like numerical simulation data.

TCAD Methodology for Design of SCR Devices for Electrostatic Discharge (ESD) Applications

Realization of on-chip electrostatic discharge (ESD) protection requires extensive technical experience and know-how. A technology computer-aided design (TCAD) methodology aimed to assist in the design and implementation of robust ESD devices is developed and presented. The methodology provides a systematic and practical means for the evaluation and optimization of ESD devices in a simulation environment. Advanced silicon-controlled-rectifier devices are considered to illustrate the approach, and experimental data measured from these devices are also included in support of the TCAD development

High-Robustness and Low-Capacitance Silicon-Controlled Rectifier for High-Speed I/O ESD Protection

A high-robustness and low-capacitance clamp for on-chip electrostatic discharge (ESD) protection is developed. The low capacitance is obtained by mitigating the capacitance associated with the lightly doped n-well/p-well junction. In addition to minimizing the capacitance, the high ESD robustness is achieved by optimizing independently within the same structure a silicon-controlled rectifier and a diode for the forward and reverse conduction processes, respectively. The new clamp with an area of 50 × 10 μm2 is able to handle an ESD current in excess of 1.5 A, whereas the capacitance at zero bias is kept at 94 fF.

Analysis of Safe Operating Area of NLDMOS and PLDMOS Transistors Subject to Transient Stresses

Transient safe operating area (TSOA) of n-type and p-type laterally diffused metal-oxide-semiconductor (LDMOS) subject to transient stresses is presented for electrostatic discharge applications. LDMOS devices connected in the gate-grounded and gate-biased configurations are stressed with 1-, 2-, 5-, 10-, and 100-ns duration transmission line pulses, and a methodology to develop an effective and accurate TSOA based on these measurements is discussed. Two-dimensional technology computer-aided design simulations are also used to discuss critical physical mechanisms governing the current conduction during the transients and the condition that finally leads to device failure beyond the TSOA.

Gate oxide evaluation under very fast transmission line pulse (VFTLP) CDM-type stress

Gate oxide breakdown is analyzed under very fast transmission line pulsed (VFTLP) stress, using different pulse - rise times and -widths. The switching of oxide behavior pre- and post- breakdown occurs in tenths of a nanosecond and it shows reproducible voltage and current characteristics. The total stress and time-dependent-dielectric-breakdown (TDDB) during pulsed stress-method are evaluated using the following two procedures: 1) by adding up the total pulsed stress time, and 2) by extrapolation of the pulsed stress time to a constant voltage stress (CVS)-type measurements. It is shown that the latter method allows for a better comparison of identical oxides TDDB under various stress conditions. A methodology to characterize gate oxide breakdown using a single pulse is finally discussed. This is important to assess the gate-oxide failure condition during a charged device model (CDM)-type electrostatic discharge (ESD).

Prediction and Modeling of Thin Gate Oxide Breakdown Subject to Arbitrary Transient Stresses

A reliable dielectric breakdown model under transient stresses via an extension of the power law is demonstrated. The model, which is based on the percolation model and the assumption of no significant detrapping, is successfully used in ramped voltage stress breakdown analysis. A demonstration of the models validity consists of applying repetitive time-variant voltage waveforms-pulses, sine waves, ramps, and noise-until breakdown and, consequently, comparing prediction to reality. The breakdown distribution is initially derived from DC measurements, with the model predicting both the center and the shape of the distribution.