Javier Ayala

Investigation of reticle defect formation at DUV lithography

Defect formation on advanced photomasks used for DUV lithography has introduced new challenges at low k1 processes industry wide. Especially at 193-nm scanner exposure, the mask pattern surface, pellicle film and the enclosed space between the pellicle and pattern surface can create a highly reactive environment. This environment can become susceptible to defect growth during repetitive exposure of a mask on DUV lithography systems due to the flow of high energy through the mask. Due to increased number of fields on the wafer, a reticle used at a 300-mm wafer fab receives roughly double the number of exposures without any cool down period, as compared to the reticles in a 200-mm wafer fab. Therefore, 193-nm lithography processes at a 300-mm wafer fab put lithographers and defect engineers into an area of untested mask behavior. During the scope of this investigation, an attenuated phase shift mask (attPSM) was periodically exposed on a 193-nm scanner and the relationship between the number of exposures (i.e., energy passed through the mask during exposures) versus defect growth was developed. Finally, chemical analysis of these defects was performed in order to understand the mechanism of this “growth”.

Defect Reduction by Nitrogen Purge of Wafer Carriers

Nitrogen purge of wafer carriers is driving defect density reduction at critical process steps. We discuss several examples of defect creation related to the environment of the semiconductor wafer and how nitrogen purge of carriers improves defect density. We have applied nitrogen purge at the gate formation, SiGe epitaxy and silicide formation process steps and we report experimental split data from in line inspection and the result at electrical test. From the impact of the nitrogen purge we can draw conclusions about the nature of defect formation. The impact on volume manufacturing is demonstrated.

Reducing Time-to-Respond in a Modern Manufacturing Environment

The complexity of modern manufacturing processes has sharply increased the number of steps affecting device and circuit performance. We discuss a number of critical steps, their control methodology and how to minimize the time to detect. Product test results and data-mining are used to identify critical steps and to determine which inline signals require most attention. The last section is devoted to optimizing the analysis of inline electrical signals and their application to tool control.

Challenges in 65nm Poly, RX and STI Defect Learning

During manufacturing transitioning from 90 nm to 65 nm node in IBMs 300 mm fab, FEOL (front end of line) defect pareto shifted as a result of the changes in integration scheme. By combining the optically based in-line inspection and electrical kerf test, key yield detractors were identified and addressed. Not all optically detected defects are true killers. Wafer functional test and physical failure analysis provided the ultimate determination for the significance of detractors.

Improving reliability through nitrogen purge of carriers

Decreasing insulator thickness at many levels of recent technology nodes raises concern for reliability. We apply a stress test inline, using a specially designed structure. It was found that reliability was strongly affected by queue time between a dry and wet etch step of a spacer, likely due to remaining RIE induced damage. By applying nitrogen purge of the wafer carrier the susceptibility to failure can be completely eliminated. This points to a fail mechanism related to residual etch products.

Using in-line film measurement as a proxy for device matching to speed up process change qualification

We describe two cases where we were able to use in-line macro measurement data to pre-select processes and to do necessary adjustments to prospect matching devices for process qualification. This approach dramatically shortens the time for new process qualification.