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Dive into the research topics where Michael D. Steigerwalt is active.

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Featured researches published by Michael D. Steigerwalt.


IEEE Transactions on Semiconductor Manufacturing | 2014

Defect Reduction by Nitrogen Purge of Wafer Carriers

Raymond Van Roijen; Pratik P. Joshi; Javier Ayala; Dane Bailey; S. Conti; William Brennan; Paul F. Findeis; Michael D. Steigerwalt

Nitrogen purge of wafer carriers is driving defect density reduction at critical process steps. We discuss several examples of defect creation related to the environment of the semiconductor wafer and how nitrogen purge of carriers improves defect density. We have applied nitrogen purge at the gate formation, SiGe epitaxy and silicide formation process steps and we report experimental split data from in line inspection and the result at electrical test. From the impact of the nitrogen purge we can draw conclusions about the nature of defect formation. The impact on volume manufacturing is demonstrated.


advanced semiconductor manufacturing conference | 2014

Ellipsometry for cSiGe Metrology

Saiqa Farhat; Srinivasan Rangarajan; Timothy J. McArdle; Michael D. Steigerwalt; Dawei Hu; Ming Dai

In this paper we report the effectiveness of optical ellipsometry in measuring thickness and Germanium % of channel SiGe on SOI substrate used in advanced node high performance semiconductor devices.


advanced semiconductor manufacturing conference | 2014

First time right deposition of embedded SiGe in new products

Raymond Van Roijen; Meghan Linskey; Eric C. Harley; Alyssa Herbert; Mohammed Fazil Fayaz; Michael Brodfuehrer; Anda C. Mocuta; Michael D. Steigerwalt; Colleen M. Snavely

Embedded SiGe, used to boost pFET performance, is grown by selective epitaxy on silicon. Pattern density effects cause the deposited thickness to be different across different product chips under otherwise identical conditions. Since device control depends critically on thickness, we apply a pattern-density based predictive growth rate, which is used as input for the existing advanced process control method. We demonstrate that the deposited layer thickness is in acceptable range for device performance across a product chip.


Archive | 2003

SOI TRENCH CAPACITOR CELL INCORPORATING A LOW-LEAKAGE FLOATING BODY ARRAY TRANSISTOR

Karen A. Bard; David M. Dobuzinsky; Herbert L. Ho; Mahendar Kumar; Denise Pendleton; Michael D. Steigerwalt; Brian Walsh


Archive | 2005

Sti formation in semiconductor device including soi and bulk silicon regions

Michael D. Steigerwalt; Mahender Kumar; Herbert L. Ho; David M. Dobuzinsky; Johnathan E. Faltermeier; Denise Pendleton


Archive | 2012

Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure

Eric C. Harley; Judson R. Holt; Dominic J. Schepis; Michael D. Steigerwalt; Linda Black; Rick Carter


Archive | 2008

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

Herbert L. Ho; Mahender Kumar; Qiqing Ouyang; Paul A. Papworth; Christopher D. Sheraw; Michael D. Steigerwalt


Archive | 2002

Surface engineering to prevent epi growth on gate poly during selective epi processing

Atul C. Ajmera; Dominic J. Schepis; Michael D. Steigerwalt


Archive | 2004

Patterning SOI with silicon mask to create box at different depths

Devendra K. Sadana; Dominic J. Schepis; Michael D. Steigerwalt


Archive | 2008

VERTICAL BIPOLAR TRANSISTOR WITH A MAJORITY CARRIER ACCUMULATION LAYER AS A SUBCOLLECTOR FOR SOI BiCMOS WITH REDUCED BURIED OXIDE THICKNESS FOR LOW-SUBSTRATE BIAS OPERATION

Herbert L. Ho; Mahender Kumar; Qiging Ouyang; Paul A. Papworth; Christopher D. Sheraw; Michael D. Steigerwalt

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