Jaya Madan

Interfacial Charge Analysis of Heterogeneous Gate Dielectric-Gate All Around-Tunnel FET for Improved Device Reliability

In this paper, we have investigated device reliability by studying the impact of interface traps, both donor (positive interface charges) and acceptor (negative interface charges), present at the Si/SiO2 interface, on analog/RF performance and linearity distortion analysis of heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET), which is used to enhance the tunneling current of TFET. Various figures of merit such as cutoff frequency fT, maximum oscillation frequency fmax, transconductance frequency product, higher order transconductance coefficients (gm1, gm3), VIP2, VIP3, IIP3, IMD3, zero crossover point, and 1-dB compression point have been investigated, and the results obtained are simultaneously compared with a gate-all-around TFET (GAA-TFET). Simulation results indicate that HDGAA-TFET is more immune toward the interface trap charges present at the Si/SiO2 interface than the GAA TFET and hence can act as a better candidate for low power switching applications. All simulations have been done on an ATLAS device simulator.

Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10−4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

Temperature Associated Reliability Issues of Heterogeneous Gate Dielectric—Gate All Around—Tunnel FET

In this work, the temperature associated reliability issues of heterogeneous gate dielectric-gate all around-tunnel FET (HD-GAA-TFET) has been addressed, and the results are simultaneously compared with gate all around tunnel FET (GAA-TFET). This is done by investigating the effect of interface trap charges such as donor (positive interface charges) and acceptor (negative interface charges) on the device figure of merits. The performance has been compared in terms of switching parameters such as ION/IOFF ratio, Iqff, Iamb, subthreshold swing (SS) and threshold voltage (Vth). Results reveal that remarkable enhancement in ION/IOFF ratio and better reliability in case of HD GAA TFET outperforms its conventional counterparts, i.e., GAA TFET. All the simulations have been done on ATLAS device simulator.

PNIN-GAA-tunnel FET with palladium catalytic metal gate as a highly sensitive hydrogen gas sensor

This work reports an n⁺ source pocket doped PIN gate all around tunnel FET (PNIN-GAA-TFET) with Palladium as a catalytic metal gate for hydrogen detection. The basis of sensing of H<inf>2</inf> molecules is the dissociation of H<inf>2</inf> into Hydrogen atoms followed by their diffusion into the Palladium (Pd) gate leading to formation of a dipole layer due to the polarization of H atoms at the Pd-SiO<inf>2</inf> interface. It is analyzed that the sensitivity of GAA-TFET based H<inf>2</inf> gas sensor is appreciably enhanced by many orders with the integration of n⁺ source pocket at the tunneling junction. Moreover, for evaluating the stability of the sensor, the performance of the sensor is analyzed at ambient temperatures other than the room temperature. Results reveal that the PNIN-GAA-TFET based H<inf>2</inf> gas sensor is practically stable for the range of ±100K w.r.t. 300K. It is examined that for the entire pressure range the sensitivity of PNIN-GAA-TFET based H<inf>2</inf> gas sensor is maximum at the room temperature.

Effect of Nanoscale Structure on Reliability of Nano Devices and Sensors

Steeper subthreshold slope and lower off-state current accessible by Tunnel FET offers great potentials in low power electronics applications. In this chapter, to enhance to a major roadblock of TFET i.e. the lower on-state current, hetero gate dielectric (HD) engineering has been amalgamated onto cylindrical gate all around GAA TFET. The reliability issues of both the devices i.e. GAA TFET and HD GAA TFET have been discussed. To study the reliability issues, at first, the effect of interface traps charge density, which are common during the pre and post-fabrication process, has been studied followed by the effect of temperature on the performance of Tunnel FET has been examined. The impact of trap density and the temperature affectability has been examined on the electrical, analog and high-frequency parameters of tunnel FET such as transfer characteristics, nonlocal Band to band tunneling rate of electrons, electric field, ambipolar current, parasitic capacitances, cut off frequency and maximum oscillation frequency. Results show that TFET exhibits weak temperature dependence for high gate bias owing to the weak dependence of band to band tunneling mechanism on temperature and for lower gate bias, the temperature dependence is large. Moreover it was analyzed that, amalgamating HD engineering scheme onto GAA TFET, along with higher ION also provides better immunity against interface trap charges in comparison with GAA TFET.