Jayanti C. Majithia

Allocation of multiport memories in data path synthesis

An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be applied to select the optimum number of buses in a multibus architecture. The method is illustrated with an example. >

Analysis of playout strategies for voice transmission using packet switching techniques

Abstract Due to variations in network delay, a stream of voice packets with deterministic interarrival times to a data network may not have deterministic interdeparture times at the destination. Two playout schemes which are designed to remove such variations in delay are considered. Analytic results for the performance of these two schemes are obtained. Numerical examples showing the effect of coefficient of variation of interdeparture time on performance are presented.

Performance analysis of a DTDMA local area network for voice and data

Abstract A Demand-oriented TDMA (Time Division Multiple Access) scheme for integrated services in a local area network (LAN) is proposed. Specifically it is designed to handle voice and transaction oriented data traffic. The topology of the network is a bus. In the proposed DTDMA scheme, the time slot assignment is a call-oriented to voice traffic and packet-oriented to data traffic. Since voice is synchronously transmitted on an implied priority basis, its performance is not affected by the data traffic on the channel. The performance of the proposed scheme has been analysed both by analytic models and simulation. It seems feasible to satisfactorily meet both voice and data performance objectives.

A new test scheduling algorithm for VLSI systems

Presents a new test scheduling algorithm based on a new heuristic approach. A new concept of time zone tree has been proposed and the algorithm builds up the tree based on a heuristic cost function. The performance of the algorithm has been compared with existing algorithms and it demonstrates encouraging results.<<ETX>>

Optimal allocation of multiport memories in datapath synthesis

In order to optimally allocate multiport memories in datapath synthesis, registers are simultaneously assigned to a configuration of several memories; this gives a more uniform distribution of register activity across the memories and usually provides a more compact assignment, allowing even fewer ports and fewer module interconnections. The LP model is extended, and a fast heuristic approach that searches for an allocation is presented. This allocation algorithm is part of a more general design tool that generates alternative multiport memory configurations and allows their rapid exploration. The designer specifies a range of design parameters, and can control the thoroughness of the search. Within the limits set by the designer, the program finds the minimum cost configuration having a feasible register allocation. The components of this system are described, and some examples of its use are presented.<<ETX>>

An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test

Minimitataon ofthe total testing time of a chip and the extra overhead involved form two key aspects in design for testability. This paper presents an integrated approach for selecting the test plans with the objective of minimizing the combined testability overhead (area and tame). The results of applicataon of the proposed technique on presynthesized datapaths are presented. Two major considerations involved with the incorporation of Built-in-Self-Test (BIST) are increase in chip area and the total test time. Attempts to reduce the area overhead amount to sharing of the hardware elements. Consequently, the scope of overlapping different tests in time is reduced. Thus, reduction of area overhead and testing time turn out to be conflicting objectives. Several algorithms exist which address the issue of scheduling the tests concurrently to minimize the total testing time [l-21. Kim et al, have addressed the issue of area optimization using the minimal set cover technique [3]. Their approach chooses a minimal set of registers to be converted to BILBO elements. The area optimization, thus obtained, is followed by the determination ofa test schedule using the approach proposed in [l]. This paper presents an integrated approach to the area/time trade-off problem, in the context of BILBO methodology. In this approach, the problem is formulated as an integer linear program (ILP) as well as a graph search problem with a heuristic cost function. The proposed cost function is used in conjunction with the well known A* algorithm [4] to obtain a solution. This heuristic approach yields “near optimal” solutions when applied to a few presynthesized circuits used as test cases. Let tij denote the j-th test plan for functional unit i. We assume that a fixed number, P, of test patterns is applied to each functional unit in the circuit. As shown in [5], the total test time Ti, required by test plan t.;j is given by Tj = Sij + (P - 1) * dij , where Sij is the number of steps in tjj and djj is the delay between two consecutive iterations of the test

Test plan generation and concurrent scheduling of tests in the presence of conflicts

When BILBO tests are being generated and scheduled, resource conflicts between I-paths and tests present many difficulties. The authors explore: how pipelining is limited by potential internal conflicts; ways to promote pipelining during test plan generation and how to incorporate a test into a test phase already containing tests that conflict with it. They do not directly address the general problems of test plan generation or test scheduling. What is offered is insight into the difficulties that (potential) conflicts provide and techniques for handling these difficulties. The insights are primarily theoretical, but the resulting techniques could be viewed as possible extensions to existing methodologies.<<ETX>>

Performance evaluation of an ethernet LAN with broadcast and point-to-point data traffic

Abstract The performance of Ethernet local area networks has been extensively reported in the literature. Major emphasis has been placed on the modification of the basic protocol to handle voice and data integration, or in the back-off and collision handling procedures. Ethernet is basically a broadcast type network and therefore has an inherent capability for handling broadcast or multicast messages. In this paper, a simple broadcast protocol is proposed which operates in the presence of normal point-to-point messages. Extensive simulation experiments have been carried out to assess the overall delay and throughput performance of a 10 Mbit/s Ethernet, with these two classes of traffic.

Access protocols for circuit/packet switching networks

Abstract This paper discusses two possible designs of access protocols for integrated computer networks with combined circuit and packet switching capabilities. The special features of these protocols are examined. Existing segregated protocols, i.e. pure circuit or packet protocols, are evaluated with future integration in mind.

Integrated approach to area-time tradeoff for built-in-self-test in VLSI circuits

The authors address the issue of area-time trade off in VLSI circuits using the BILBO methodology of BIST. The issue has been dealt with in an integrated manner. Two distinct approaches, integer linear programming and graph theoretic have been presented.<<ETX>>