Thomas Charles Wilson

An integrated approach to retargetable code generation

Special-purpose instruction set processors (ISPs) challenge compilers because of instruction level parallelism, small numbers of registers, and highly specialized register capabilities. Many traditionally separate subproblems in code generation have been unified and jointly optimized within a single integer linear programming (ILP) model. ILP modeling provides a powerful methodology for generating high-quality code for a variety of ISPs.<<ETX>>

An ILP solution for simultaneous scheduling, allocation, and binding in multiple block synthesis

Presents a novel approach to the high-level synthesis problems of scheduling, allocation, and binding for multiblock behavioral descriptions. Our design tool, JOSHUA, uses an integer linear programming (ILP) formulation to solve the three interdependent subproblems simultaneously and optimally. The system allows the designer to minimize time, area, and the number of microwords for the entire design, or for specific segments of the design. A diverse module library provides a selection of modules that can perform a specific operation in differing amounts of time (control steps). A novel feature is the ability to select an implementation for part of an algorithm from among a set of implementation alternatives. The system can also handle the issues of path frequencies, loops, parallel threads of execution, and register allocation.<<ETX>>

An ILP-Based Approach to Code Generation

Generating efficient code for instruction-set processors involves many different, interrelated subproblems. Several aspects of the problem have been integrated within a single, powerful integer linear programming (ILP) model. We present the central concepts of the model and its application. We also explain the organization and function of a complete code generation system that is currently under development and that surrounds and supports an ILP optimizer. This system contains many optimization modules that can either perform optimizations on their own or present promising opportunities for the ILP to consider.

AN ENHANCED GENETIC ALGORITHM FOR SOLVING THE HIGH-LEVEL SYNTHESIS PROBLEMS OF SCHEDULING, ALLOCATION, AND BINDING

This paper presents a novel approach to the concurrent solution of three High-Level Synthesis (HLS) problems that are modeled as a Constraint-Satisfaction Problem (CSP) and solved using an Enhanced Genetic Algorithm (EGA). We focus on the core problems of high-level synthesis: Scheduling, Allocation, and Binding. Scheduling consists of assigning of operations in a Data-Flow Graph (DFG) to control steps or clock cycles. Allocation selects specific numbers and types of functional units from a hardware library to perform the operations specified in the DFG. Binding assigns constituent operations of the DFG to specific unit instances. A very general version of this problem is considered where functional units may perform different operations in different numbers of control steps. The EGA is designed to solve CSPs quickly and does not require a user to specify appropriate mutation and crossover rates a priori; these are determined automatically during the course of the genetic search. The enhancements include a directed mutation operator and a new type of elitism that avoids premature convergence. The HLS problems are solved by applying two EGAs in a hierarchical manner. The first performs allocation, while the second performs scheduling and binding and serves as the fitness function for the second. When compared to other, well-known techniques, our results show a reduction in time to obtain optimal solutions for standard benchmarks.

Instruction-set matching and GA-based selection for embedded-processor code generation

The core tasks of retargetable code generation are instruction-set matching and selection for a given application program and a DSP/ASIP processor. In this paper, we utilize a model of target architecture specification that employs both behavioral and structural information, to facilitate this process. The matching method is based on a pattern tree structure of instructions. This tree structure, generated automatically, is implemented by using a pattern queue and a flag table. The matching process is efficient since it bypasses many patterns in the tree which do not match at certain nodes in the DFG of given application program. Two genetic algorithms are implemented for pattern selection: a pure GA which uses standard GA operators, and a GA with backtracking which employs variable-length chromesomes. Optimal or near-optimal pattern selection is obtained in a reasonable period of time for a wide range of application programs.

A new test scheduling algorithm for VLSI systems

Presents a new test scheduling algorithm based on a new heuristic approach. A new concept of time zone tree has been proposed and the algorithm builds up the tree based on a heuristic cost function. The performance of the algorithm has been compared with existing algorithms and it demonstrates encouraging results.<<ETX>>

Optimal allocation of multiport memories in datapath synthesis

In order to optimally allocate multiport memories in datapath synthesis, registers are simultaneously assigned to a configuration of several memories; this gives a more uniform distribution of register activity across the memories and usually provides a more compact assignment, allowing even fewer ports and fewer module interconnections. The LP model is extended, and a fast heuristic approach that searches for an allocation is presented. This allocation algorithm is part of a more general design tool that generates alternative multiport memory configurations and allows their rapid exploration. The designer specifies a range of design parameters, and can control the thoroughness of the search. Within the limits set by the designer, the program finds the minimum cost configuration having a feasible register allocation. The components of this system are described, and some examples of its use are presented.<<ETX>>

An enhanced genetic solution for scheduling, module allocation, and binding in VLSI design

This paper presents a novel approach to the high-level synthesis problems of scheduling, module allocation, and module binding for behavioral descriptions. A very general version of this problem is considered where modules may perform different operations in different numbers of control steps. These inherently interdependent problems are solved using an Enhanced Genetic Algorithm (EGA) which is both more robust and more efficient than the simple GA.

An Integrated and Accelerated ILP Solution for Scheduling, Module Allocation, and Binding in Datapath Synthesis

We present an optimum and integrated solution to the problems of scheduling, allocation, and binding using an integer linear program (UP) that minimizes a weighted sum of module area and total ezecution time under very general assumptions of module capability. Two important eztensions are the use of pipelined functional units and operator chaining. The version of the ILP presented accelerates the solution in various ways.

An Approach to Minimize Testability Overhead for BILBO based Built-In-Self-Test

Minimitataon ofthe total testing time of a chip and the extra overhead involved form two key aspects in design for testability. This paper presents an integrated approach for selecting the test plans with the objective of minimizing the combined testability overhead (area and tame). The results of applicataon of the proposed technique on presynthesized datapaths are presented. Two major considerations involved with the incorporation of Built-in-Self-Test (BIST) are increase in chip area and the total test time. Attempts to reduce the area overhead amount to sharing of the hardware elements. Consequently, the scope of overlapping different tests in time is reduced. Thus, reduction of area overhead and testing time turn out to be conflicting objectives. Several algorithms exist which address the issue of scheduling the tests concurrently to minimize the total testing time [l-21. Kim et al, have addressed the issue of area optimization using the minimal set cover technique [3]. Their approach chooses a minimal set of registers to be converted to BILBO elements. The area optimization, thus obtained, is followed by the determination ofa test schedule using the approach proposed in [l]. This paper presents an integrated approach to the area/time trade-off problem, in the context of BILBO methodology. In this approach, the problem is formulated as an integer linear program (ILP) as well as a graph search problem with a heuristic cost function. The proposed cost function is used in conjunction with the well known A* algorithm [4] to obtain a solution. This heuristic approach yields “near optimal” solutions when applied to a few presynthesized circuits used as test cases. Let tij denote the j-th test plan for functional unit i. We assume that a fixed number, P, of test patterns is applied to each functional unit in the circuit. As shown in [5], the total test time Ti, required by test plan t.;j is given by Tj = Sij + (P - 1) * dij , where Sij is the number of steps in tjj and djj is the delay between two consecutive iterations of the test