Dilip K. Banerji

Allocation of multiport memories in data path synthesis

An algorithm to synthesize registers using multiport memories during data-path synthesis is presented. The proposed approach considers not only the access requirements of registers but also their interconnection to operators in order to minimize required interconnections. The same approach can be applied to select the optimum number of buses in a multibus architecture. The method is illustrated with an example. >

On Control Memory Minimization in Microprogrammed Digital Computers

The problem of minimizing the bit dimension of control memories in microprogrammed digital computers is considered in this paper. We start essentially with the same basic formulation as that of Grasselli and Montanari [2]. However, in order to minimize the computational requirements, we start directly with the set of maximum compatibility classes of microcommands whose number is usually small, and readily obtain near-minimal irredundant solutions. A minimal solution is then obtained from the irredundant solutions.

An integrated approach to retargetable code generation

Special-purpose instruction set processors (ISPs) challenge compilers because of instruction level parallelism, small numbers of registers, and highly specialized register capabilities. Many traditionally separate subproblems in code generation have been unified and jointly optimized within a single integer linear programming (ILP) model. ILP modeling provides a powerful methodology for generating high-quality code for a variety of ISPs.<<ETX>>

Sign Detection in Residue Number Systems

This paper is concerned with the sign detection problem in residue number systems. The proposed solution is applicable only to nonredundant systems. It is shown that under rather general conditions an explicit, closed formula for the sign function can be obtained. In a special case, when one of the moduli is 2, the sign function becomes an EXCLUSIVE-OR function. A sign detection algorithm is proposed and methods of implementing the algorithm are presented.

A hierarchical architecture for detecting selfish behaviour in community wireless mesh networks

Wireless mesh networks (WMNs) consist of dedicated nodes called mesh routers which relay the traffic generated by mesh clients over multi-hop paths. In a community WMN, all mesh routers may not be managed by an Internet Service Provider (ISP). Limited capacity of wireless channels and lack of a single trusted authority in such networks can motivate mesh routers to behave selfishly by dropping relay traffic in order to provide a higher throughput to their own users. Existing solutions for stimulating cooperation in multi-hop networks use promiscuous monitoring or exchange probe packets to detect selfish nodes and apply virtual currency mechanism to compensate the cooperating nodes. These schemes fail to operate well when applied to WMNs which have a multi-radio environment with a relatively static topology. In this paper we, propose architecture for a community WMN which can detect selfish behaviour in the network and enforce cooperation among mesh routers. The architecture adopts a decentralized detection scheme by dividing the mesh routers into manageable clusters. Monitoring agents hosted on managed mesh routers monitor the behaviour of mesh routers in their cluster by collecting periodic reports and sending them to the sink agents hosted at the mesh gateways. To make the detection more accurate we consider the quality of wireless links. We present experimental results that evaluate the performance of our scheme.

An ILP solution for simultaneous scheduling, allocation, and binding in multiple block synthesis

Presents a novel approach to the high-level synthesis problems of scheduling, allocation, and binding for multiblock behavioral descriptions. Our design tool, JOSHUA, uses an integer linear programming (ILP) formulation to solve the three interdependent subproblems simultaneously and optimally. The system allows the designer to minimize time, area, and the number of microwords for the entire design, or for specific segments of the design. A diverse module library provides a selection of modules that can perform a specific operation in differing amounts of time (control steps). A novel feature is the ability to select an implementation for part of an algorithm from among a set of implementation alternatives. The system can also handle the issues of path frequencies, loops, parallel threads of execution, and register allocation.<<ETX>>

On Translation Algorithms in Residue Number Systems

This paper considers translation problems in residue number systems. The conversion from a fixed-base representation to a residue representation can be done using residue adders only; we show that relatively simple combinational logic can be used to replace one level of residue addition. In the reverse translation problem, we examine the conditions under which base extension can be used to compute the fixed-base digits from a residue code number, and we study the efficiency of the algorithm.

An ILP-Based Approach to Code Generation

Generating efficient code for instruction-set processors involves many different, interrelated subproblems. Several aspects of the problem have been integrated within a single, powerful integer linear programming (ILP) model. We present the central concepts of the model and its application. We also explain the organization and function of a complete code generation system that is currently under development and that surrounds and supports an ILP optimizer. This system contains many optimization modules that can either perform optimizations on their own or present promising opportunities for the ILP to consider.

Hierarchical FPGA placement

Field-programmable gate arrays (FPGAs) are semiconductor chips that can realize most digital circuits on site by specifying programmable logic and their interconnections. The use of FPGAs has grown almost exponentially because they dramatically reduce design turnaround time and startup cost for electronic products compared with traditional application-specific integrated circuits (ASICs). Efficient computer-aided-design tools are required to compile hardware descriptions into bitstream files that are used to configure the target FPGA to implement the desired circuits. Currently, the compile time, which is dominated by placement and routing time, can easily be hours or even days for large (8-million-gate) FPGAs. With 40-million-gate FPGAs on the horizon, these prohibitively long compile times may nullify the time-to-market advantage of FPGAs. This paper presents two novel placement heuristics that significantly reduce the computation time required to achieve high-quality placements, compared with the versatile place and route (VPR) tool. The first algorithm is an enhancement of simulated annealing (SA) that attempts to solve the placement problem top-down by considering all modules at the flat level. The second algorithm involves a hierarchical approach based on a two-step procedure that first proceeds bottom-up (grouping highly connected modules together) and then top-down (declustering). The overall effect is to reduce the number of entities needing to be considered at each level, such that time-consuming methods like SA become feasible for very large problems. Experimental results show a 70¿80% reduction in runtime, coupled with very high-quality placements.

Routability prediction for hierarchical FPGAs

This paper investigates the problem of routability prediction in a FPGA that employs a hierarchical routing architecture. Such a FPGA is called a hierarchical FPGA (HFPGA). A novel model is proposed to analyze various HFPGA configurations. A software tool has been developed to predict the routability of circuits on specific HFPGA architectures. Primary contribution of this work is that routability prediction can be done immediately after the technology-mapping step, rather than after placement. The effect of connection block and switch block flexibility on routability is also studied. The results show that compared to a symmetrical FPGA architecture we can achieve the same degree of routability on a HFPGA, with much fewer routing switches.